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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>nRF52833 Development Kit Hardware Questions</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/61222/nrf52833-development-kit-hardware-questions</link><description>Hi there, 
 I have a few questions regarding the Development Kit hardware design. I just bought up the polygon pour manager. I noticed that all layers except Mid-Layer 2 are netted to GND. What does ‘VDD_SAM’ allude to in the Mid-Layer 2 polygon pour</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Thu, 14 May 2020 09:28:35 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/61222/nrf52833-development-kit-hardware-questions" /><item><title>RE: nRF52833 Development Kit Hardware Questions</title><link>https://devzone.nordicsemi.com/thread/249880?ContentTypeID=1</link><pubDate>Thu, 14 May 2020 09:28:35 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:ab8c2804-1deb-46da-acda-cf897e8a27d6</guid><dc:creator>cheezballs</dc:creator><description>[quote userid="73427" url="~/f/nordic-q-a/61222/nrf52833-development-kit-hardware-questions/249495"]Midtlayer 2 is the power plane of the board. VDD_SAM refers to the power domain for the Segger debugger chip used in the DK (ATSAM3U2CA).[/quote]
&lt;p&gt;This makes sense, thank you!&lt;/p&gt;
[quote userid="73427" url="~/f/nordic-q-a/61222/nrf52833-development-kit-hardware-questions/249495"]Our reference designs show what the distribution of the via holes may look like, or think about having one ground via every 3-5 mm.[/quote]
&lt;p&gt;Thanks for clarifying that!&amp;nbsp;I am using one of the nRF52833 reference designs at the moment.&lt;/p&gt;
[quote userid="73427" url="~/f/nordic-q-a/61222/nrf52833-development-kit-hardware-questions/249495"]Also you can take a look at this blogpost with general PCB design guidelines for the nRF52 series[/quote]
&lt;p&gt;This looks like a really useful resource.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Many thanks&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF52833 Development Kit Hardware Questions</title><link>https://devzone.nordicsemi.com/thread/249495?ContentTypeID=1</link><pubDate>Tue, 12 May 2020 13:24:10 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:997a7b72-3532-43fa-a0f4-a8af4a90d795</guid><dc:creator>Marjeris Romero</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;Midtlayer 2 is the power plane of the board. VDD_SAM refers to the power domain for the Segger debugger chip used in the DK (ATSAM3U2CA).&lt;/p&gt;
&lt;p&gt;And yes, it&amp;#39;s recommended to use enough ground vias to connect the ground planes. This is specially important for RF designs, where having a big solid ground plane is very important. Our reference designs show what the distribution of the via holes may look like, or think about having one ground via every 3-5 mm.&lt;/p&gt;
&lt;p&gt;If you are planing to do your own custom PCB using one of our nRF chips I recommend taking a look at the reference schematics and layout corresponding to the chip you are using. You can find these on the Nordic Infocenter, for example for the nRF52833 take a look at: &lt;a href="https://infocenter.nordicsemi.com/index.jsp?topic=%2Fps_nrf52833%2Fref_circuitry.html"&gt;https://infocenter.nordicsemi.com/index.jsp?topic=%2Fps_nrf52833%2Fref_circuitry.html&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;Pay close attention to the section &amp;quot;PCB guidelines&amp;quot; above.&lt;/p&gt;
&lt;p&gt;Also you can take a look at this blogpost with general PCB design guidelines for the nRF52 series: &lt;a href="https://devzone.nordicsemi.com/nordic/short-range-guides/b/hardware-and-layout/posts/general-pcb-design-guidelines-for-nrf52"&gt;https://devzone.nordicsemi.com/nordic/short-range-guides/b/hardware-and-layout/posts/general-pcb-design-guidelines-for-nrf52&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;Best regards,&lt;/p&gt;
&lt;p&gt;Marjeris&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>