SPI Master high speed behavior, gapless transmission

RE: SPI Master high speed behavior, gapless transmission

Sam — Fri, 20 Mar 2015 20:22:06 GMT

The 8MHz timings are holding across at least 20 words, but I'm not sure about production reliability (personally I think we'll just stick to 4MHz if the ordering issue is safe) Someone from Nordic commented that 8MHz was "unusable," was just wondering if this was still true for current versions of the chip: devzone.nordicsemi.com/.../

RE: SPI Master high speed behavior, gapless transmission

Sam — Fri, 20 Mar 2015 20:21:55 GMT

Yeah, got it to work gapless at 8MHz with some optimized assembler with some really sketchy stuff. Not enough clocks to actually clear the EVENT_READY flag...I just get the timings exactly right that it never over or underflows. Gotta double check some of the timings to confirm (it's been a while since I've done a lot of ARM assembly, and I'm not as familiar with the M0 nuances). Goes without saying that if an interrupt happens, I'm in trouble. BTW it's half duplex right now, which allows me to cheat a bit more and save an instruction. It's not a standard SPI slave. I've got an older Saleae that runs at 24MHz, and it's at max sample rate--it's actually clear that it captures everything when you zoom in, but I think the 16MHz/24MHz clocks produce some jitter because they're not multiples of each other.

RE: SPI Master high speed behavior, gapless transmission

RK — Fri, 20 Mar 2015 07:29:37 GMT

Order of RX and TX doesn't matter. Do whichever first you wish to do first, once you get the EVENT_READY there's a slot to write the TXD, that's what you need. As long as you do clear the event and read RXD as well, you're good - you won't get another event until you do those things.

8MHz is settable and is reliable if you could guarantee to feed the TX buffer at that speed. At 8MHz you have 16 CPU cycles per byte output, if you can guarantee in the worst case to read the event, get a byte, put it into TXD, clear the event, read RXD and increment your pointer all within 16 CPU cycles then 8MHz should work. With a really simple data buffer and some assembly I guess that's possible, but only just. Newer chips won't change that, not unless the processor frequency is increased. What would be better would be a DMA for SPI master, but there isn't one, not yet.

Where's the requirement for gapless transmission coming from? Most (all?) SPI slaves I've so far come across are fine with gaps. You'll have problems with gapless if you have anything else going on, an interrupt firing for a timer or particularly the softdevice which is going to interrupt you when it feels like it.

Oh and if that's a Saleae trace, try capturing at a higher sample rate, looks like you are missing occasional transitions. I can get my Saleae to capture 8MHz SPI bursts by running it at full sampling speed.