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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Use of Non-Eval Board Custom Hardware</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/61469/use-of-non-eval-board-custom-hardware</link><description>All of our initial BLE project development has been done using a the Nordic nRF5_SDK_15.3.0_59ac345 SDK and 10056 eval board. Now we have a production board that is based on the eval board but has the following differences: (1) no reset PB, (2) no SPI</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Mon, 18 May 2020 19:24:04 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/61469/use-of-non-eval-board-custom-hardware" /><item><title>RE: Use of Non-Eval Board Custom Hardware</title><link>https://devzone.nordicsemi.com/thread/250539?ContentTypeID=1</link><pubDate>Mon, 18 May 2020 19:24:04 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:563b5910-9893-487d-9ae4-a0450e1a0a14</guid><dc:creator>DKarnes</dc:creator><description>&lt;p&gt;Thanks.&amp;nbsp; Fixing the clock and related items fixed it.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Use of Non-Eval Board Custom Hardware</title><link>https://devzone.nordicsemi.com/thread/250370?ContentTypeID=1</link><pubDate>Mon, 18 May 2020 08:09:18 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:42c0549e-9389-404d-aef7-68a00f8491ba</guid><dc:creator>Karl Ylvisaker</dc:creator><description>&lt;p&gt;Hello,&lt;br /&gt;&lt;br /&gt;As Jörg mentions, the SRAM address points to &lt;a href="https://infocenter.nordicsemi.com/index.jsp?topic=%2Fps_nrf52840%2Fclock.html&amp;amp;anchor=register.EVENTS_LFCLKSTARTED"&gt;EVENTS_LFCLKSTARTED&lt;/a&gt;, which suggests that you clock configuration is incorrect. I suspect that it is the LFCLK source that is the error.&lt;br /&gt;How have you configured your LFCLK source? Is it anything like the following?&lt;br /&gt;&lt;br /&gt;&lt;pre class="ui-code" data-mode="c_cpp"&gt;// &amp;lt;h&amp;gt; Clock - SoftDevice clock configuration

 

//==========================================================
// &amp;lt;o&amp;gt; NRF_SDH_CLOCK_LF_SRC  - SoftDevice clock source.
 
// &amp;lt;0=&amp;gt; NRF_CLOCK_LF_SRC_RC 
// &amp;lt;1=&amp;gt; NRF_CLOCK_LF_SRC_XTAL 
// &amp;lt;2=&amp;gt; NRF_CLOCK_LF_SRC_SYNTH 

 

#ifndef NRF_SDH_CLOCK_LF_SRC
#define NRF_SDH_CLOCK_LF_SRC 0
#endif

 

// &amp;lt;o&amp;gt; NRF_SDH_CLOCK_LF_RC_CTIV - SoftDevice calibration timer interval. 
#ifndef NRF_SDH_CLOCK_LF_RC_CTIV
#define NRF_SDH_CLOCK_LF_RC_CTIV 16
#endif

 

// &amp;lt;o&amp;gt; NRF_SDH_CLOCK_LF_RC_TEMP_CTIV - SoftDevice calibration timer interval under constant temperature. 
// &amp;lt;i&amp;gt; How often (in number of calibration intervals) the RC oscillator shall be calibrated
// &amp;lt;i&amp;gt;  if the temperature has not changed.

 

#ifndef NRF_SDH_CLOCK_LF_RC_TEMP_CTIV
#define NRF_SDH_CLOCK_LF_RC_TEMP_CTIV 2
#endif

 

// &amp;lt;o&amp;gt; NRF_SDH_CLOCK_LF_ACCURACY  - External clock accuracy used in the LL to compute timing.
 
// &amp;lt;0=&amp;gt; NRF_CLOCK_LF_ACCURACY_250_PPM 
// &amp;lt;1=&amp;gt; NRF_CLOCK_LF_ACCURACY_500_PPM 
// &amp;lt;2=&amp;gt; NRF_CLOCK_LF_ACCURACY_150_PPM 
// &amp;lt;3=&amp;gt; NRF_CLOCK_LF_ACCURACY_100_PPM 
// &amp;lt;4=&amp;gt; NRF_CLOCK_LF_ACCURACY_75_PPM 
// &amp;lt;5=&amp;gt; NRF_CLOCK_LF_ACCURACY_50_PPM 
// &amp;lt;6=&amp;gt; NRF_CLOCK_LF_ACCURACY_30_PPM 
// &amp;lt;7=&amp;gt; NRF_CLOCK_LF_ACCURACY_20_PPM 
// &amp;lt;8=&amp;gt; NRF_CLOCK_LF_ACCURACY_10_PPM 
// &amp;lt;9=&amp;gt; NRF_CLOCK_LF_ACCURACY_5_PPM 
// &amp;lt;10=&amp;gt; NRF_CLOCK_LF_ACCURACY_2_PPM 
// &amp;lt;11=&amp;gt; NRF_CLOCK_LF_ACCURACY_1_PPM 

 

#ifndef NRF_SDH_CLOCK_LF_ACCURACY
#define NRF_SDH_CLOCK_LF_ACCURACY 1
#endif&lt;/pre&gt;&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;Best regards,&lt;br /&gt;Karl&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Use of Non-Eval Board Custom Hardware</title><link>https://devzone.nordicsemi.com/thread/250300?ContentTypeID=1</link><pubDate>Sat, 16 May 2020 18:36:23 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:f9c47409-c070-4df4-81b9-e71a7f8e0b9c</guid><dc:creator>Turbo J</dc:creator><description>[quote userid="89965" url="~/f/nordic-q-a/61469/use-of-non-eval-board-custom-hardware"]SRAM address 0x40000104[/quote]
&lt;p&gt;That is peripherial address space and not simply SRAM. Looking into the PS, this is the EVENTS_LFCLKSTARTED address.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;In other words, your clock config is still wrong. Search this forum, questions about clock config pop up all the time here.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>