RE: DPPI Clock Synchronization/Jitter

Hung Bui — Wed, 03 Jun 2020 12:16:46 GMT

Hi Abram,

The DPPI system on the nRF53 is a little bit more complex than the PPI on the nRF52. Here the information I got from our designers:

One 16 MHz cycle is correct for 53-series as well, but may be higher in two situations:

When the event comes from the 32 kHz source (watchdog, rtc) and the rest of the core is inactive/sleeping
Events from the other core via IPC, while the receiving core is inactive/sleeping

Under those two exceptions, additional delay to start up the HF clock and regulators will come in addition. If users wants to have predictable latency, we have this constant latency mode that can be used to avoid the HFCLOCK stopping, thus ensuring a one 16 MHz clock cycle. (this is similar to nRF52).

This info will be included in the final Product Spec.

In your case the TIMER would need HFCLOCK running all the time, so setting the mode constant latency TASKS_CONSTLAT = 1 will not cause any drawback and you will have the max jitter to 1 16MHz clock cycle.