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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>VDD decoupling caps maximum values</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/62464/vdd-decoupling-caps-maximum-values</link><description>Hello, 
 I read your white paper nWP-030 about selecting the decouping caps. But I didn&amp;#39;t find any explanation why you also specify maximum values for the caps. Especially C VDD effective capacitance 5.5 uF max. would be a little problematic as we are</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Fri, 24 Jul 2020 09:33:45 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/62464/vdd-decoupling-caps-maximum-values" /><item><title>RE: VDD decoupling caps maximum values</title><link>https://devzone.nordicsemi.com/thread/261548?ContentTypeID=1</link><pubDate>Fri, 24 Jul 2020 09:33:45 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:4180a365-0b10-4b5c-9efb-09730d33b602</guid><dc:creator>Andreas</dc:creator><description>&lt;p&gt;Hi John,&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;There is some derating in the capacitors, see this whitepaper:&amp;nbsp;&lt;a href="https://infocenter.nordicsemi.com/topic/nwp_030/WP/nwp_030/intro.html?cp=14_3"&gt;https://infocenter.nordicsemi.com/topic/nwp_030/WP/nwp_030/intro.html?cp=14_3&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Best regards,&lt;/p&gt;
&lt;p&gt;Andreas&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: VDD decoupling caps maximum values</title><link>https://devzone.nordicsemi.com/thread/261495?ContentTypeID=1</link><pubDate>Fri, 24 Jul 2020 05:27:03 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:fcae8ec0-471c-4b0f-80db-e14c76ff0d60</guid><dc:creator>John Man</dc:creator><description>&lt;p&gt;Hi Andreas,&lt;/p&gt;
&lt;p&gt;Per Datasheet, CVDD is requested in the range of 2.7~5.5uF. However, the reference design (configuration No. 5 schematic) shows that the total VDD nominal capacitance is 4.7uF+1uF=5.7uF. This already violates the CVDD requirement. Can you let me know if CVDD requirement is valid or the reference schematic is valid-----they are in contradiction.&lt;/p&gt;
&lt;p&gt;Thanks&lt;/p&gt;
&lt;p&gt;John&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: VDD decoupling caps maximum values</title><link>https://devzone.nordicsemi.com/thread/261330?ContentTypeID=1</link><pubDate>Thu, 23 Jul 2020 09:25:32 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:a48d2129-0269-4d18-8623-c14d0c338dbc</guid><dc:creator>Andreas</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;With config 4 both VDD and DEC4 are regulator outputs and inputs, meaning both VDD and DEC4 must be withing the specified range.&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Best regards,&lt;/p&gt;
&lt;p&gt;Andreas&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: VDD decoupling caps maximum values</title><link>https://devzone.nordicsemi.com/thread/261298?ContentTypeID=1</link><pubDate>Thu, 23 Jul 2020 06:48:07 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:f4853f73-1b02-43df-b604-1f0263837d2a</guid><dc:creator>wallance.lin</dc:creator><description>&lt;p&gt;Hi Andreas&lt;/p&gt;
&lt;p&gt;thanks! I would like to check which one or both of them could cause power supply system issue?&amp;nbsp;&lt;br /&gt;&lt;span&gt;Over maximum Effective capacitance in VDD or &amp;nbsp;lower than&amp;nbsp;minimum Effective capacitance in DEC4?&amp;nbsp;&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: VDD decoupling caps maximum values</title><link>https://devzone.nordicsemi.com/thread/260806?ContentTypeID=1</link><pubDate>Mon, 20 Jul 2020 13:13:00 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:1b6321df-cfda-4ac2-bacf-781c7f23faad</guid><dc:creator>Andreas</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;This is outside spec, and could cause the power supply system to not behave according to spec.&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Best regards,&lt;/p&gt;
&lt;p&gt;Andreas&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: VDD decoupling caps maximum values</title><link>https://devzone.nordicsemi.com/thread/260288?ContentTypeID=1</link><pubDate>Thu, 16 Jul 2020 08:15:38 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:2e2e86f3-4da8-47ca-a26a-dbdcfa6f86e0</guid><dc:creator>wallance.lin</dc:creator><description>&lt;p&gt;Hi&lt;/p&gt;
&lt;p&gt;I&amp;#39;m using nRF52840 and also find the same issue after checking nWP-030, our design follows &amp;quot;7.3.4 Circuit configuration no. 4 from nRF52840 datasheet&amp;quot;. after considering tolerance, we find&lt;/p&gt;
&lt;p&gt;1. the maximum effective Vdd cap is 7.11uF &amp;gt; 5.5uF(maximum Effective capacitance in VDD), &lt;/p&gt;
&lt;p&gt;2. the minimum capacitance of Cdec4 is 0.68uF &amp;lt; 0.7uF (minimum Effective capacitance in DEC4),&lt;/p&gt;
&lt;p&gt;do you have any concern for this? and where we need pay attention or check?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: VDD decoupling caps maximum values</title><link>https://devzone.nordicsemi.com/thread/254603?ContentTypeID=1</link><pubDate>Fri, 12 Jun 2020 07:00:24 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:e2fb1b25-7d2f-4c54-9185-943c1cb26607</guid><dc:creator>Andreas</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;This is the capacitive load the REG0 is designed for and is thus only relevant for the power configurations where REG0 is used (supply on VDDH). The capacitance on the main supply pin (VDDH for high-voltage config and VDD+VDDH for normal voltage config) can exceed this.&lt;/p&gt;
&lt;p&gt;As for the FEM, note that the REG0 can deliver a maximum of 25mA when nRF52840 TX power &amp;lt; 0 dBm, I would assume your FEM draws a bit more than this. In this case you should not supply the FEM from the VDD rail anyway.&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Best regards,&lt;/p&gt;
&lt;p&gt;Andreas&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>