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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Using 16MHz SPIM on nRF5340-PDK</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/62533/using-16mhz-spim-on-nrf5340-pdk</link><description>I have SPIM working at 8MHz on nRF5340-PDK 
 I want to increase the SPIM speed to 16MHz. 
 The errata for nRF5340 states &amp;quot;In 128 MHz mode, SPIM max receive frequency is 16 Mbps. In 64 MHz mode, SPIM max receive frequency is 8 Mbps.&amp;quot; 
 So I need to increase</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Wed, 17 Jun 2020 12:28:36 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/62533/using-16mhz-spim-on-nrf5340-pdk" /><item><title>RE: Using 16MHz SPIM on nRF5340-PDK</title><link>https://devzone.nordicsemi.com/thread/255528?ContentTypeID=1</link><pubDate>Wed, 17 Jun 2020 12:28:36 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:269a97f6-97ab-4ead-ba66-3bcd27c2364b</guid><dc:creator>Sigurd</dc:creator><description>[quote user="DTurnbow"]Is there a sample program that uses&amp;nbsp;nrfx_clock_divider_set()?[/quote]
&lt;p&gt;&amp;nbsp;I don&amp;#39;t see any sample code that uses this (as of today).&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
[quote user="DTurnbow"]Are there only some pins that allow extra high drive?[/quote]
&lt;p&gt;&amp;nbsp;Correct.&amp;nbsp;Some pins may not support every drive configuration. See this chapter:&amp;nbsp;&lt;a href="https://infocenter.nordicsemi.com/index.jsp?topic=%2Fps_nrf5340%2Fchapters%2Fpin.html"&gt;https://infocenter.nordicsemi.com/index.jsp?topic=%2Fps_nrf5340%2Fchapters%2Fpin.html&lt;/a&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Using 16MHz SPIM on nRF5340-PDK</title><link>https://devzone.nordicsemi.com/thread/255268?ContentTypeID=1</link><pubDate>Tue, 16 Jun 2020 13:05:49 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:882fd877-721e-4334-b878-9aaa5a4835bc</guid><dc:creator>DBT</dc:creator><description>&lt;p&gt;Thanks Sigurd.&lt;/p&gt;
&lt;p&gt;Both these hints were helpful.&lt;/p&gt;
&lt;p&gt;Is there a sample program that uses&amp;nbsp;nrfx_clock_divider_set()?&amp;nbsp; When I tried to use it I got some build errors so I ended up using the&amp;nbsp;NRF_CLOCK_NS-&amp;gt;HFCLKCTRL code directly.&lt;/p&gt;
&lt;p&gt;I switched to SPIM4 and the dedicated SPIM4 pins and was able to get it to work.&amp;nbsp; It looked like I might need to setup the SPI pins to use high drive instead of standard drive for 16MHz operation.&lt;/p&gt;
&lt;p&gt;I noticed that the datasheet mentions there is an extra high drive option as well, but when I tried to set the PIN_CNF[] register to use extra high drive it didn&amp;#39;t work (at least in SES).&amp;nbsp; Are there only some pins that allow extra high drive?&lt;/p&gt;
&lt;p&gt;(I tried to set PIN_CNF[8] to 0x00000B01)&lt;/p&gt;
&lt;p&gt;&lt;img height="314" src="https://devzone.nordicsemi.com/resized-image/__size/320x240/__key/communityserver-discussions-components-files/4/pastedimage1592312681965v1.png" width="537" alt=" " /&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Using 16MHz SPIM on nRF5340-PDK</title><link>https://devzone.nordicsemi.com/thread/255072?ContentTypeID=1</link><pubDate>Mon, 15 Jun 2020 14:50:31 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:aa7790a4-d489-4935-8309-940fa593b140</guid><dc:creator>Sigurd</dc:creator><description>[quote user=""]On a non-secure build, this causes some kind of repeating reset.&amp;nbsp; Can you tell me why?[/quote]
&lt;p&gt;Try using&amp;nbsp;&lt;span&gt;NRF_CLOCK_NS, and not&amp;nbsp;NRF_CLOCK_S&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;Note that we have a function called&amp;nbsp;&lt;span&gt;nrfx_clock_divider_set() for this.&amp;nbsp;&lt;a href="https://github.com/nrfconnect/sdk-hal_nordic/blob/v1.3.0-rc1/nrfx/drivers/src/nrfx_clock.c#L400"&gt;https://github.com/nrfconnect/sdk-hal_nordic/blob/v1.3.0-rc1/nrfx/drivers/src/nrfx_clock.c#L400&lt;/a&gt;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;What SPI MASTER instance are you using ? Note that only SPI master 4 is high-speed. See &lt;a href="https://infocenter.nordicsemi.com/topic/ps_nrf5340/spim.html?cp=3_0_0_6_29_6#topic"&gt;this link&lt;/a&gt;.&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>