nRF52840 SWD

RE: nRF52840 SWD

Jørgen Holmefjord — Thu, 02 Jul 2020 15:00:20 GMT

If you are using a standalone Segger J-Link debugger and its V_TRef is higher than expected when not downloading/debugging the chip, you will have to check this with Segger support.

RE: nRF52840 SWD

Poki Huang — Mon, 29 Jun 2020 05:48:18 GMT

Hi Jorgen:

It is custom board not DK, we use external J-Line device(segger J-Link, https://goods.ruten.com.tw/item/show?21311175219003)

And we directly connect 2V1, SWDIO, SWDCLK, SOC_RESET to segger J-Link.

Poki

RE: nRF52840 SWD

Jørgen Holmefjord — Wed, 24 Jun 2020 16:22:44 GMT

Is this on a custom board or on a nRF52840 DK? Are you using the on-board debugger of a DK, or do you use an external J-Link device (if so, which one)? Can you post the schematics showing how the debugger is connected to the nRF/board?

RE: nRF52840 SWD

Poki Huang — Wed, 24 Jun 2020 08:17:49 GMT

Hi Turbo:

Because we found when connect to J-Link, when we download image, measure V_TRef voltage is VDD(we provide 2.1V to nRF VDD), this is ok. But when not download image, the V_TRef become 2.85V, and we disconnect J-Link and nRF, measure V_TRef is 3V, seems when not download image, the V_TRef will not follow VDD. We afraid this will damage our PMIC, so want add level shifter.

RE: nRF52840 SWD

Turbo J — Wed, 24 Jun 2020 07:21:46 GMT

[quote userid="89143" url="~/f/nordic-q-a/62963/nrf52840-swd"] level shifter between J-Link[/quote]

Why? Commercial J-Links have level shifters included - that is why you need V_TRef connected to VCC on the NRF chip.