RE: Strange MOSI behaviour on SPI2(Mode 0)(Data not ready on sampling clock)

Stefan Tsenev — Sat, 04 Jul 2020 18:06:44 GMT

Thank you for the hint.

It seems that I have misread the specs for ST7789 and following you comment I made a test on 250kHz with analogue channel to find my mistake(The pin could be 3-state in some cases).

It is clearly visible that MOSI is driven high but on the other side is pulled low until the clock appears:

Kind regards,

Stefan

RE: Strange MOSI behaviour on SPI2(Mode 0)(Data not ready on sampling clock)

hmolesworth — Sat, 04 Jul 2020 17:43:12 GMT

Try this:

    APP_ERROR_CHECK(nrf_drv_spi_init(&spi, &spi_config, spi_event_handler, NULL));
    // Boost drive to MOSI and MCLK to sharpen clock edges and timing
    nrf_gpio_cfg(TFT_MOSI, NRF_GPIO_PIN_DIR_OUTPUT, NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_H0H1, NRF_GPIO_PIN_NOSENSE);
    nrf_gpio_cfg(TFT_MCLK, NRF_GPIO_PIN_DIR_OUTPUT, NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_H0H1, NRF_GPIO_PIN_NOSENSE);
}

The reason is that the logic analyser/'scope is hiding information from you, the edges are really not as sharp as displayed and the timing is too sloppy with S0S1 drive levels at 8MHz