<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Quick check of my SPI code &amp;amp; a few related questions</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/63680/quick-check-of-my-spi-code-a-few-related-questions</link><description>Hi, I&amp;#39;ve began making a SPI module for programming a PIC16. It only transmits data, so two pins. My questions are: 1. any obvious errors? 2. does the EVENTS_ENDTX occur when the double buffer is empty? I need to ensure the cpu is a step ahead of the buffer</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Thu, 16 Jul 2020 08:07:10 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/63680/quick-check-of-my-spi-code-a-few-related-questions" /><item><title>RE: Quick check of my SPI code &amp; a few related questions</title><link>https://devzone.nordicsemi.com/thread/260287?ContentTypeID=1</link><pubDate>Thu, 16 Jul 2020 08:07:10 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:e712ce66-7c3f-4484-95fc-dc6a7cefe5d7</guid><dc:creator>snoopy20</dc:creator><description>&lt;p&gt;Can close this one, the other SPI thread I have is more relevant now.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Quick check of my SPI code &amp; a few related questions</title><link>https://devzone.nordicsemi.com/thread/260272?ContentTypeID=1</link><pubDate>Thu, 16 Jul 2020 06:29:24 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:7ec112f4-47e3-419b-83cc-e0c3fa681d6b</guid><dc:creator>Susheel Nuguru</dc:creator><description>&lt;p&gt;Nothing seems to be configured with SPI CONFIG and FREQUENCY register. I am not sure if the peer is responding anything to these bytes. Can you see if there is any meaninful reception from the peer through the logic analyzer?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Quick check of my SPI code &amp; a few related questions</title><link>https://devzone.nordicsemi.com/thread/259980?ContentTypeID=1</link><pubDate>Tue, 14 Jul 2020 17:47:16 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:eb82b33a-2c63-41ad-986c-b114da6abf70</guid><dc:creator>snoopy20</dc:creator><description>&lt;p&gt;I&amp;#39;ve went back and updated the code to use EVENT_READY which I&amp;#39;d missed.&lt;br /&gt;&lt;br /&gt;So far:&lt;br /&gt;&lt;br /&gt;1. configure pins and turn on SPI(M) (I&amp;#39;m not using input)&lt;br /&gt;&lt;br /&gt;&lt;pre class="ui-code" data-mode="c_cpp"&gt; NRF_GPIO-&amp;gt;PIN_CNF[CFG_PIN_GLUE_DAT] = pinDisconnectInputBuffer | (GPIO_PIN_CNF_DIR_Output &amp;lt;&amp;lt; GPIO_PIN_CNF_DIR_Pos);
 NRF_GPIO-&amp;gt;PIN_CNF[CFG_PIN_GLUE_CLK] = (GPIO_PIN_CNF_DIR_Output &amp;lt;&amp;lt; GPIO_PIN_CNF_DIR_Pos);

 NRF_SPIM0-&amp;gt;PSEL.SCK = CFG_PIN_GLUE_CLK;
 NRF_SPIM0-&amp;gt;PSEL.MOSI = CFG_PIN_GLUE_DAT;
 NRF_SPIM0-&amp;gt;PSEL.MISO = SPIM_PSEL_MOSI_CONNECT_Disconnected &amp;lt;&amp;lt; SPIM_PSEL_MOSI_CONNECT_Pos;
 NRF_SPIM0-&amp;gt;ENABLE = SPIM_ENABLE_ENABLE_Enabled &amp;lt;&amp;lt; SPIM_ENABLE_ENABLE_Pos;

&lt;/pre&gt;&lt;/p&gt;
&lt;p&gt;2. Fill buffer and wait&lt;br /&gt;&lt;br /&gt;&lt;pre class="ui-code" data-mode="c_cpp"&gt;  NRF_SPI0-&amp;gt;TXD = &amp;#39;M&amp;#39;;
  NRF_SPI0-&amp;gt;TXD = &amp;#39;C&amp;#39;;
  while (! NRF_SPI0-&amp;gt;EVENTS_READY) {}
  NRF_SPI0-&amp;gt;EVENTS_READY = 0;&lt;/pre&gt;&lt;br /&gt;&lt;br /&gt;Unfortunately the EVENTS_READY doesn&amp;#39;t reach 1 so I&amp;#39;m stuck.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Quick check of my SPI code &amp; a few related questions</title><link>https://devzone.nordicsemi.com/thread/259908?ContentTypeID=1</link><pubDate>Tue, 14 Jul 2020 12:30:37 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:f4b6d9bd-d735-4b73-9ab7-4bff098325eb</guid><dc:creator>snoopy20</dc:creator><description>&lt;p&gt;That&amp;#39;s correct I don&amp;#39;t want EasyDMA for this operation.&lt;/p&gt;
&lt;p&gt;&lt;br /&gt;The question now is how to keep the double buffer filled up.&lt;br /&gt;&lt;br /&gt;If I write to NRF_SPI0-&amp;gt;TXD twice what to check to see that NRF_SPI0-&amp;gt;TXD is empty (transfered into double buffer) to keep one step ahead of it emptying?&lt;br /&gt;&lt;br /&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Quick check of my SPI code &amp; a few related questions</title><link>https://devzone.nordicsemi.com/thread/259899?ContentTypeID=1</link><pubDate>Tue, 14 Jul 2020 12:00:27 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:e26e51d1-7047-4e59-aa3b-32dec88ecca7</guid><dc:creator>Susheel Nuguru</dc:creator><description>&lt;p&gt;You seems to be using the SPI functionality with the SPIM0 register context. This is a bit confusing.&lt;/p&gt;
&lt;p&gt;If you do not want to use the EasyDMA, then use NRF_SPI0 registers which do not have EVENTS_ENDTX. If you want to use the EasyDMA then I think the generation of EVENTS_ENDTX is dependent on the MAXTX setting. I haven&amp;#39;t tried mixing the concept of SPIM and SPI even though they are in the same seriobox instance. So not sure if your code is correct or not.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>