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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>QSPI issue/questions</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/63902/qspi-issue-questions</link><description>Hey everyone, I&amp;#39;m trying to use the QSPI module (again) to interface to RAM, not FLASH. I&amp;#39;m not really sure if this is possible, but we&amp;#39;ll get there. Right now I can&amp;#39;t get it to initialize. 
 
 So far I can&amp;#39;t even get the qspi module to initilize, nrfx_qspi_init</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Tue, 21 Jul 2020 18:00:46 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/63902/qspi-issue-questions" /><item><title>RE: QSPI issue/questions</title><link>https://devzone.nordicsemi.com/thread/261068?ContentTypeID=1</link><pubDate>Tue, 21 Jul 2020 18:00:46 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:715ddae5-78a4-4597-a3db-75de0814176e</guid><dc:creator>Adam Gerken</dc:creator><description>&lt;p&gt;That stinks. I&amp;#39;ll probably just revert to SPIM mode. I wish the QSPI module was more flexible. Thanks.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: QSPI issue/questions</title><link>https://devzone.nordicsemi.com/thread/261063?ContentTypeID=1</link><pubDate>Tue, 21 Jul 2020 17:33:26 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:8f85efa0-bc1b-4443-a81f-a41c74580f38</guid><dc:creator>haakonsh</dc:creator><description>&lt;p&gt;I think that&amp;#39;s a hard one.&amp;nbsp;&lt;br /&gt;&lt;br /&gt;The only solution I can think of is to manipulate the CLK and I/O lines with GPIOs during the instruction/command phase.&amp;nbsp;&lt;br /&gt;That would require an external multiplexer between the QSPI and RAM device.&lt;br /&gt;The idea is to mask the first 6 clock cycles and injecting the instructions on the last 2.&amp;nbsp;&lt;br /&gt;&lt;br /&gt;It might require execution priority on the CPU during that time in order to bit-bang the instruction.&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: QSPI issue/questions</title><link>https://devzone.nordicsemi.com/thread/261038?ContentTypeID=1</link><pubDate>Tue, 21 Jul 2020 16:02:08 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:ce82e62f-f2ad-4f4b-91c1-1ee74b9f5879</guid><dc:creator>Adam Gerken</dc:creator><description>&lt;p&gt;Alright Haakonsh, I think I ran into a game stopper. The RAM wants the commands sent on all four data lines not just one, which I don&amp;#39;t see how to make happen. Any ideas?&lt;/p&gt;
&lt;p&gt;RAM:&lt;/p&gt;
&lt;p&gt;&lt;img src="https://devzone.nordicsemi.com/resized-image/__size/320x240/__key/communityserver-discussions-components-files/4/pastedimage1595347223812v1.png" alt=" " /&gt;&lt;/p&gt;
&lt;p&gt;NRF:&lt;/p&gt;
&lt;p&gt;&lt;img src="https://devzone.nordicsemi.com/resized-image/__size/320x240/__key/communityserver-discussions-components-files/4/pastedimage1595347254705v2.png" alt=" " /&gt;&lt;/p&gt;
&lt;p&gt;RAM:&lt;/p&gt;
&lt;p&gt;&lt;img src="https://devzone.nordicsemi.com/resized-image/__size/320x240/__key/communityserver-discussions-components-files/4/pastedimage1595347283848v3.png" alt=" " /&gt;&lt;/p&gt;
&lt;p&gt;NRF:&lt;/p&gt;
&lt;p&gt;&lt;img src="https://devzone.nordicsemi.com/resized-image/__size/320x240/__key/communityserver-discussions-components-files/4/pastedimage1595347324516v4.png" alt=" " /&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: QSPI issue/questions</title><link>https://devzone.nordicsemi.com/thread/260867?ContentTypeID=1</link><pubDate>Mon, 20 Jul 2020 15:59:19 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:fcc7f546-e384-4d86-aff0-08f945d579a2</guid><dc:creator>Shahar</dc:creator><description>&lt;p&gt;The nrf_qpsi which I suggested to use are the QSPI_HAL btw...&lt;br /&gt;&lt;br /&gt;I suggested to take nrfx_qspi and as the template - as it&amp;#39;ll give structure, and most of the stuff might be ready already (just strip away anything to do with Flash, like erase, etc.)&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: QSPI issue/questions</title><link>https://devzone.nordicsemi.com/thread/260866?ContentTypeID=1</link><pubDate>Mon, 20 Jul 2020 15:57:26 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:6fc2f411-9acc-450b-84ab-2af94d26e69f</guid><dc:creator>Adam Gerken</dc:creator><description>&lt;p&gt;Haakonsh, That&amp;#39;s what I&amp;#39;m thinking too. I&amp;#39;ll plug away on it and let you know if I run into any issues.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: QSPI issue/questions</title><link>https://devzone.nordicsemi.com/thread/260840?ContentTypeID=1</link><pubDate>Mon, 20 Jul 2020 14:30:12 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:fdf4fd1a-cba4-4c5a-9288-d33ce4c5cc22</guid><dc:creator>haakonsh</dc:creator><description>&lt;p&gt;I suggest you use the&amp;nbsp;&lt;a title="QSPI HAL" href="https://infocenter.nordicsemi.com/topic/sdk_nrf5_v17.0.0/group__nrf__qspi__hal.html?cp=7_1_6_8_0_26_2"&gt;QSPI HAL&lt;/a&gt;&amp;nbsp;directly and write your RAM driver on top of that. The&amp;nbsp;&lt;a title="QSPI driver" href="https://infocenter.nordicsemi.com/topic/sdk_nrf5_v17.0.0/group__nrfx__qspi.html?cp=7_1_6_8_0_26_1"&gt;QSPI driver&lt;/a&gt;&amp;nbsp;is written for FLASH devices and you will have to remove most of the code from it anyways in order to port it to RAM.&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: QSPI issue/questions</title><link>https://devzone.nordicsemi.com/thread/260663?ContentTypeID=1</link><pubDate>Fri, 17 Jul 2020 19:47:38 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:1da5059c-2837-4050-9369-bb35c6964637</guid><dc:creator>Shahar</dc:creator><description>&lt;p&gt;An interesting question.&lt;/p&gt;
&lt;p&gt;AFAIK you are correct assuming the nrfx_qspi module is only for handling QSPI flash module, and expects the module to respond to the QSPI op codes.&lt;/p&gt;
&lt;p&gt;But I don&amp;#39;t think there&amp;#39;s any&amp;nbsp;limitation on you taking the nrfx_qspi, renaming it, and modifying the code to utilize the nrf_qspi functions with your new op codes.&lt;/p&gt;
&lt;p&gt;You&amp;#39;ll probably only need to implement read and write, and&amp;nbsp;maybe&amp;nbsp;KISS by having everything done in blocking mode (as it&amp;#39;s RAM ... and maybe no need for erase or long write/read operations)&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>