I2C communication problem with nRF9160

RE: I2C communication problem with nRF9160

Kenneth — Thu, 17 Sep 2020 11:23:21 GMT

I believe the board file enable i2c2 by default, from nrf9160dk_nrf9160_common.dts I can find:

&i2c2 {
    compatible = "nordic,nrf-twim";
    status = "okay";
    sda-pin = <30>;
    scl-pin = <31>;
};

Based on this I think you should override this in your overlay file by:

&i2c2 {
    status = "disabled";
};

RE: I2C communication problem with nRF9160

duxinglang — Thu, 17 Sep 2020 02:38:55 GMT

O my gad! I did find I2C_1 and I2C_2 enabled in this file, but in fact I only enabled I2C_1, not I2C_2. Who started I2C_2 automatically?

#define CONFIG_LOG_DEFAULT_LEVEL 3
#define CONFIG_SB_VALIDATION_INFO_MAGIC 0x86518483
#define CONFIG_SB_VALIDATION_POINTER_MAGIC 0x6919b47e
#define CONFIG_SB_VALIDATION_INFO_CRYPTO_ID 1
#define CONFIG_SB_VALIDATION_INFO_VERSION 2
#define CONFIG_SB_VALIDATION_METADATA_OFFSET 0
#define CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE 2048
#define CONFIG_SPM 1
#define CONFIG_SPM_BUILD_STRATEGY_FROM_SOURCE 1
#define CONFIG_ARM_ENTRY_VENEERS_LIB_NAME "spm/libspmsecureentries.a"
#define CONFIG_FW_INFO 1
#define CONFIG_FW_INFO_OFFSET 0x200
#define CONFIG_FW_INFO_FIRMWARE_VERSION 1
#define CONFIG_FW_INFO_MAGIC_COMMON 0x281ee6de
#define CONFIG_FW_INFO_MAGIC_FIRMWARE_INFO 0x8fcebb4c
#define CONFIG_FW_INFO_MAGIC_EXT_API 0xb845acea
#define CONFIG_FW_INFO_HARDWARE_ID 91
#define CONFIG_FW_INFO_VERSION 2
#define CONFIG_FW_INFO_CRYPTO_ID 0
#define CONFIG_FW_INFO_MAGIC_COMPATIBILITY_ID 0
#define CONFIG_FW_INFO_MAGIC_LEN 12
#define CONFIG_FW_INFO_VALID_VAL 0x9102FFFF
#define CONFIG_EXT_API_PROVIDE_EXT_API_UNUSED 1
#define CONFIG_MPSL_THREAD_COOP_PRIO 8
#define CONFIG_MPSL_SIGNAL_STACK_SIZE 1024
#define CONFIG_MPSL_LOG_LEVEL_INF 1
#define CONFIG_MPSL_LOG_LEVEL 3
#define CONFIG_BSD_LIBRARY 1
#define CONFIG_BSD_LIBRARY_SYS_INIT 1
#define CONFIG_NRF91_SOCKET_BLOCK_LIMIT 2048
#define CONFIG_AT_CMD 1
#define CONFIG_AT_CMD_SYS_INIT 1
#define CONFIG_AT_CMD_INIT_PRIORITY 40
#define CONFIG_AT_CMD_THREAD_PRIO 10
#define CONFIG_AT_CMD_THREAD_STACK_SIZE 1024
#define CONFIG_AT_CMD_RESPONSE_MAX_LEN 2700
#define CONFIG_AT_CMD_RESPONSE_BUFFER_COUNT 2
#define CONFIG_AT_CMD_LOG_LEVEL_INF 1
#define CONFIG_AT_CMD_LOG_LEVEL 3
#define CONFIG_NRF_SPU_FLASH_REGION_SIZE 0x8000
#define CONFIG_AT_NOTIF 1
#define CONFIG_AT_NOTIF_SYS_INIT 1
#define CONFIG_AT_NOTIF_LOG_LEVEL_INF 1
#define CONFIG_AT_NOTIF_LOG_LEVEL 3
#define CONFIG_DK_LIBRARY 1
#define CONFIG_DK_LIBRARY_BUTTON_SCAN_INTERVAL 10
#define CONFIG_DK_LIBRARY_INVERT_BUTTONS 1
#define CONFIG_DK_LIBRARY_DYNAMIC_BUTTON_HANDLERS 1
#define CONFIG_DK_LIBRARY_LOG_LEVEL_INF 1
#define CONFIG_DK_LIBRARY_LOG_LEVEL 3
#define CONFIG_AT_CMD_PARSER 1
#define CONFIG_MODEM_INFO 1
#define CONFIG_MODEM_INFO_MAX_AT_PARAMS_RSP 10
#define CONFIG_MODEM_INFO_BUFFER_SIZE 128
#define CONFIG_MODEM_INFO_ADD_NETWORK 1
#define CONFIG_MODEM_INFO_ADD_DATE_TIME 1
#define CONFIG_MODEM_INFO_ADD_SIM 1
#define CONFIG_MODEM_INFO_ADD_SIM_ICCID 1
#define CONFIG_MODEM_INFO_ADD_SIM_IMSI 1
#define CONFIG_MODEM_INFO_ADD_DEVICE 1
#define CONFIG_MODEM_INFO_ADD_BOARD 1
#define CONFIG_RESET_ON_FATAL_ERROR 1
#define CONFIG_FATAL_ERROR_LOG_LEVEL_INF 1
#define CONFIG_FATAL_ERROR_LOG_LEVEL 3
#define CONFIG_ENTROPY_CC310 1
#define CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL 1
#define CONFIG_MCUBOOT_CMAKELISTS_DIR "$MCUBOOT_BASE/boot/zephyr/"
#define CONFIG_MCUBOOT_BUILD_STRATEGY_FROM_SOURCE 1
#define CONFIG_MCUBOOT_IMAGE_VERSION "0.0.0+0"
#define CONFIG_BOOT_SIGNATURE_KEY_FILE "root-rsa-2048.pem"
#define CONFIG_DT_FLASH_WRITE_BLOCK_SIZE 4
#define CONFIG_BSD_LIB 1
#define CONFIG_NRFXLIB_CRYPTO 1
#define CONFIG_NRF_OBERON 1
#define CONFIG_HAS_NRFX 1
#define CONFIG_NRFX_NVMC 1
#define CONFIG_NRFX_SPIM 1
#define CONFIG_NRFX_SPIM3 1
#define CONFIG_NRFX_TWIM 1
#define CONFIG_NRFX_TWIM1 1
#define CONFIG_SPI 1
#define CONFIG_I2C 1
#define CONFIG_NET_IPV6 1
#define CONFIG_BOARD "nrf9160_pca10090"
#define CONFIG_I2C_2 1
#define CONFIG_SPI_3 1
#define CONFIG_FLASH_LOAD_SIZE 0x40000
#define CONFIG_FLASH_LOAD_OFFSET 0x40000
#define CONFIG_SOC "nRF9160_SICA"
#define CONFIG_SOC_SERIES "nrf91"
#define CONFIG_NUM_IRQS 65
#define CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC 32768
#define CONFIG_GPIO 1
#define CONFIG_SYS_POWER_MANAGEMENT 1
#define CONFIG_HAS_SYS_POWER_STATE_DEEP_SLEEP_1 1
#define CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT 1
#define CONFIG_CLOCK_CONTROL 1
#define CONFIG_NRF_RTC_TIMER 1
#define CONFIG_SYS_CLOCK_TICKS_PER_SEC 32768
#define CONFIG_BUILD_OUTPUT_HEX 1
#define CONFIG_FLOAT 1
#define CONFIG_TEXT_SECTION_OFFSET 0x0
#define CONFIG_FLASH_SIZE 1024
#define CONFIG_FLASH_BASE_ADDRESS 0x0
#define CONFIG_SRAM_SIZE 128
#define CONFIG_SRAM_BASE_ADDRESS 0x20020000
#define CONFIG_SOC_GECKO_EMU 1
#define CONFIG_HEAP_MEM_POOL_SIZE 16384
#define CONFIG_BOARD_NRF9160_PCA10090NS 1
#define CONFIG_SOC_SERIES_NRF91X 1
#define CONFIG_CPU_HAS_ARM_MPU 1
#define CONFIG_CPU_HAS_NRF_IDAU 1
#define CONFIG_NRF_SPU_RAM_REGION_SIZE 0x2000
#define CONFIG_SOC_FAMILY "nordic_nrf"
#define CONFIG_SOC_FAMILY_NRF 1
#define CONFIG_HAS_HW_NRF_CC310 1
#define CONFIG_HAS_HW_NRF_CLOCK 1
#define CONFIG_HAS_HW_NRF_DPPIC 1
#define CONFIG_HAS_HW_NRF_EGU0 1
#define CONFIG_HAS_HW_NRF_EGU1 1
#define CONFIG_HAS_HW_NRF_EGU2 1
#define CONFIG_HAS_HW_NRF_EGU3 1
#define CONFIG_HAS_HW_NRF_EGU4 1
#define CONFIG_HAS_HW_NRF_EGU5 1
#define CONFIG_HAS_HW_NRF_GPIO0 1
#define CONFIG_HAS_HW_NRF_GPIOTE 1
#define CONFIG_HAS_HW_NRF_I2S 1
#define CONFIG_HAS_HW_NRF_IPC 1
#define CONFIG_HAS_HW_NRF_PDM 1
#define CONFIG_HAS_HW_NRF_POWER 1
#define CONFIG_HAS_HW_NRF_PWM0 1
#define CONFIG_HAS_HW_NRF_PWM1 1
#define CONFIG_HAS_HW_NRF_PWM2 1
#define CONFIG_HAS_HW_NRF_PWM3 1
#define CONFIG_HAS_HW_NRF_RTC0 1
#define CONFIG_HAS_HW_NRF_RTC1 1
#define CONFIG_HAS_HW_NRF_SAADC 1
#define CONFIG_HAS_HW_NRF_SPIM0 1
#define CONFIG_HAS_HW_NRF_SPIM1 1
#define CONFIG_HAS_HW_NRF_SPIM2 1
#define CONFIG_HAS_HW_NRF_SPIM3 1
#define CONFIG_HAS_HW_NRF_SPIS0 1
#define CONFIG_HAS_HW_NRF_SPIS1 1
#define CONFIG_HAS_HW_NRF_SPIS2 1
#define CONFIG_HAS_HW_NRF_SPIS3 1
#define CONFIG_HAS_HW_NRF_SPU 1
#define CONFIG_HAS_HW_NRF_TIMER0 1
#define CONFIG_HAS_HW_NRF_TIMER1 1
#define CONFIG_HAS_HW_NRF_TIMER2 1
#define CONFIG_HAS_HW_NRF_TWIM0 1
#define CONFIG_HAS_HW_NRF_TWIM1 1
#define CONFIG_HAS_HW_NRF_TWIM2 1
#define CONFIG_HAS_HW_NRF_TWIM3 1
#define CONFIG_HAS_HW_NRF_TWIS0 1
#define CONFIG_HAS_HW_NRF_TWIS1 1
#define CONFIG_HAS_HW_NRF_TWIS2 1
#define CONFIG_HAS_HW_NRF_TWIS3 1
#define CONFIG_HAS_HW_NRF_UARTE0 1
#define CONFIG_HAS_HW_NRF_UARTE1 1
#define CONFIG_HAS_HW_NRF_UARTE2 1
#define CONFIG_HAS_HW_NRF_UARTE3 1
#define CONFIG_HAS_HW_NRF_WDT 1
#define CONFIG_NRF_ENABLE_ICACHE 1
#define CONFIG_SOC_NRF9160 1
#define CONFIG_SOC_NRF9160_SICA 1
#define CONFIG_SOC_LOG_LEVEL_INF 1
#define CONFIG_SOC_LOG_LEVEL 3
#define CONFIG_SOC_COMPATIBLE_NRF 1
#define CONFIG_CPU_CORTEX 1
#define CONFIG_CPU_CORTEX_M 1
#define CONFIG_ISA_THUMB2 1
#define CONFIG_STACK_ALIGN_DOUBLE_WORD 1
#define CONFIG_PLATFORM_SPECIFIC_INIT 1
#define CONFIG_FAULT_DUMP 2
#define CONFIG_BUILTIN_STACK_GUARD 1
#define CONFIG_ARM_STACK_PROTECTION 1
#define CONFIG_ARM_NONSECURE_FIRMWARE 1
#define CONFIG_ARM_FIRMWARE_USES_SECURE_ENTRY_FUNCS 1
#define CONFIG_FP_HARDABI 1
#define CONFIG_CPU_CORTEX_M33 1
#define CONFIG_CPU_CORTEX_M_HAS_SYSTICK 1
#define CONFIG_CPU_CORTEX_M_HAS_DWT 1
#define CONFIG_CPU_CORTEX_M_HAS_BASEPRI 1
#define CONFIG_CPU_CORTEX_M_HAS_VTOR 1
#define CONFIG_CPU_CORTEX_M_HAS_SPLIM 1
#define CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS 1
#define CONFIG_CPU_CORTEX_M_HAS_CMSE 1
#define CONFIG_ARMV7_M_ARMV8_M_MAINLINE 1
#define CONFIG_ARMV8_M_MAINLINE 1
#define CONFIG_ARMV8_M_SE 1
#define CONFIG_ARMV7_M_ARMV8_M_FP 1
#define CONFIG_ARMV8_M_DSP 1
#define CONFIG_XIP 1
#define CONFIG_GEN_ISR_TABLES 1
#define CONFIG_GEN_IRQ_VECTOR_TABLE 1
#define CONFIG_ARM_MPU 1
#define CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE 32
#define CONFIG_MPU_ALLOW_FLASH_WRITE 1
#define CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE 32
#define CONFIG_ARM_TRUSTZONE_M 1
#define CONFIG_ARCH "arm"
#define CONFIG_ARM 1
#define CONFIG_ARCH_LOG_LEVEL_INF 1
#define CONFIG_ARCH_LOG_LEVEL 3
#define CONFIG_MPU_LOG_LEVEL_INF 1
#define CONFIG_MPU_LOG_LEVEL 3
#define CONFIG_TRUSTED_EXECUTION_NONSECURE 1
#define CONFIG_HW_STACK_PROTECTION 1
#define CONFIG_PRIVILEGED_STACK_SIZE 1024
#define CONFIG_PRIVILEGED_STACK_TEXT_AREA 256
#define CONFIG_KOBJECT_TEXT_AREA 256
#define CONFIG_GEN_SW_ISR_TABLE 1
#define CONFIG_ARCH_SW_ISR_TABLE_ALIGN 0
#define CONFIG_GEN_IRQ_START_VECTOR 0
#define CONFIG_ARCH_HAS_TRUSTED_EXECUTION 1
#define CONFIG_ARCH_HAS_STACK_PROTECTION 1
#define CONFIG_ARCH_HAS_USERSPACE 1
#define CONFIG_ARCH_HAS_EXECUTABLE_PAGE_BIT 1
#define CONFIG_ARCH_HAS_RAMFUNC_SUPPORT 1
#define CONFIG_ARCH_HAS_NESTED_EXCEPTION_DETECTION 1
#define CONFIG_ARCH_HAS_THREAD_ABORT 1
#define CONFIG_CPU_HAS_TEE 1
#define CONFIG_CPU_HAS_FPU 1
#define CONFIG_CPU_HAS_MPU 1
#define CONFIG_MEMORY_PROTECTION 1
#define CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS 1
#define CONFIG_MPU_GAP_FILLING 1
#define CONFIG_FP_SHARING 1
#define CONFIG_KERNEL_LOG_LEVEL_INF 1
#define CONFIG_KERNEL_LOG_LEVEL 3
#define CONFIG_MULTITHREADING 1
#define CONFIG_NUM_COOP_PRIORITIES 16
#define CONFIG_NUM_PREEMPT_PRIORITIES 15
#define CONFIG_MAIN_THREAD_PRIORITY 0
#define CONFIG_COOP_ENABLED 1
#define CONFIG_PREEMPT_ENABLED 1
#define CONFIG_PRIORITY_CEILING 0
#define CONFIG_NUM_METAIRQ_PRIORITIES 0
#define CONFIG_MAIN_STACK_SIZE 8192
#define CONFIG_IDLE_STACK_SIZE 320
#define CONFIG_ISR_STACK_SIZE 2048
#define CONFIG_THREAD_STACK_INFO 1
#define CONFIG_ERRNO 1
#define CONFIG_SCHED_DUMB 1
#define CONFIG_WAITQ_DUMB 1
#define CONFIG_BOOT_BANNER 1
#define CONFIG_BOOT_DELAY 0
#define CONFIG_SYSTEM_WORKQUEUE_PRIORITY -1
#define CONFIG_OFFLOAD_WORKQUEUE_STACK_SIZE 1024
#define CONFIG_OFFLOAD_WORKQUEUE_PRIORITY -1
#define CONFIG_ATOMIC_OPERATIONS_BUILTIN 1
#define CONFIG_TIMESLICING 1
#define CONFIG_TIMESLICE_SIZE 0
#define CONFIG_TIMESLICE_PRIORITY 0
#define CONFIG_POLL 1
#define CONFIG_NUM_MBOX_ASYNC_MSGS 10
#define CONFIG_NUM_PIPE_ASYNC_MSGS 10
#define CONFIG_HEAP_MEM_POOL_MIN_SIZE 64
#define CONFIG_ARCH_HAS_CUSTOM_SWAP_TO_MAIN 1
#define CONFIG_SWAP_NONATOMIC 1
#define CONFIG_SYS_CLOCK_EXISTS 1
#define CONFIG_KERNEL_INIT_PRIORITY_OBJECTS 30
#define CONFIG_KERNEL_INIT_PRIORITY_DEFAULT 40
#define CONFIG_KERNEL_INIT_PRIORITY_DEVICE 50
#define CONFIG_APPLICATION_INIT_PRIORITY 90
#define CONFIG_STACK_POINTER_RANDOM 0
#define CONFIG_MP_NUM_CPUS 1
#define CONFIG_TICKLESS_IDLE 1
#define CONFIG_TICKLESS_IDLE_THRESH 3
#define CONFIG_TICKLESS_KERNEL 1
#define CONFIG_SYS_PM_POLICY_RESIDENCY 1
#define CONFIG_SYS_PM_MIN_RESIDENCY_DEEP_SLEEP_1 60000
#define CONFIG_SYS_PM_LOG_LEVEL_INF 1
#define CONFIG_SYS_PM_LOG_LEVEL 3
#define CONFIG_HAS_DTS 1
#define CONFIG_HAS_DTS_GPIO 1
#define CONFIG_HAS_DTS_I2C 1
#define CONFIG_UART_CONSOLE_ON_DEV_NAME "UART_0"
#define CONFIG_CONSOLE 1
#define CONFIG_CONSOLE_INPUT_MAX_LINE_LEN 128
#define CONFIG_CONSOLE_HAS_DRIVER 1
#define CONFIG_UART_CONSOLE 1
#define CONFIG_UART_CONSOLE_INIT_PRIORITY 60
#define CONFIG_UART_CONSOLE_LOG_LEVEL_INF 1
#define CONFIG_UART_CONSOLE_LOG_LEVEL 3
#define CONFIG_SERIAL 1
#define CONFIG_SERIAL_HAS_DRIVER 1
#define CONFIG_SERIAL_SUPPORT_ASYNC 1
#define CONFIG_SERIAL_SUPPORT_INTERRUPT 1
#define CONFIG_UART_NRFX 1
#define CONFIG_UART_0_NRF_UARTE 1
#define CONFIG_UART_0_NRF_TX_BUFFER_SIZE 32
#define CONFIG_NRF_UARTE_PERIPHERAL 1
#define CONFIG_SYSTEM_CLOCK_DISABLE 1
#define CONFIG_SYSTEM_CLOCK_INIT_PRIORITY 0
#define CONFIG_TICKLESS_CAPABLE 1
#define CONFIG_ENTROPY_GENERATOR 1
#define CONFIG_ENTROPY_NRF_FORCE_ALT 1
#define CONFIG_ENTROPY_HAS_DRIVER 1
#define CONFIG_ENTROPY_NAME "ENTROPY_0"
#define CONFIG_GPIO_LOG_LEVEL_INF 1
#define CONFIG_GPIO_LOG_LEVEL 3
#define CONFIG_GPIO_NRFX 1
#define CONFIG_GPIO_NRF_INIT_PRIORITY 40
#define CONFIG_GPIO_NRF_P0 1
#define CONFIG_SPI_INIT_PRIORITY 70
#define CONFIG_SPI_LOG_LEVEL_INF 1
#define CONFIG_SPI_LOG_LEVEL 3
#define CONFIG_SPI_2 1
#define CONFIG_SPI_2_OP_MODES 1
#define CONFIG_SPI_3_OP_MODES 1
#define CONFIG_SPI_NRFX 1
#define CONFIG_SPI_3_NRF_SPIM 1
#define CONFIG_SPI_3_NRF_ORC 0xff
#define CONFIG_SPI_NRFX_RAM_BUFFER_SIZE 0
#define CONFIG_I2C_NRFX 1
#define CONFIG_I2C_1_NRF_TWIM 1
#define CONFIG_I2C_INIT_PRIORITY 60
#define CONFIG_I2C_LOG_LEVEL_INF 1
#define CONFIG_I2C_LOG_LEVEL 3
#define CONFIG_I2C_1 1
#define CONFIG_CLOCK_CONTROL_LOG_LEVEL_INF 1
#define CONFIG_CLOCK_CONTROL_LOG_LEVEL 3
#define CONFIG_CLOCK_CONTROL_NRF 1
#define CONFIG_CLOCK_CONTROL_NRF_K32SRC_20PPM 1
#define CONFIG_FLASH_HAS_DRIVER_ENABLED 1
#define CONFIG_FLASH_HAS_PAGE_LAYOUT 1
#define CONFIG_FLASH 1
#define CONFIG_FLASH_LOG_LEVEL_INF 1
#define CONFIG_FLASH_LOG_LEVEL 3
#define CONFIG_FLASH_PAGE_LAYOUT 1
#define CONFIG_SOC_FLASH_NRF 1
#define CONFIG_NEWLIB_LIBC 1
#define CONFIG_HAS_NEWLIB_LIBC_NANO 1
#define CONFIG_NEWLIB_LIBC_NANO 1
#define CONFIG_STDOUT_CONSOLE 1
#define CONFIG_POSIX_MAX_FDS 4
#define CONFIG_MAX_TIMER_COUNT 5
#define CONFIG_UPDATEHUB_LOG_LEVEL_INF 1
#define CONFIG_UPDATEHUB_LOG_LEVEL 3
#define CONFIG_PRINTK 1
#define CONFIG_EARLY_CONSOLE 1
#define CONFIG_ASSERT 1
#define CONFIG_ASSERT_LEVEL 2
#define CONFIG_SPIN_VALIDATE 1
#define CONFIG_ASSERT_VERBOSE 1
#define CONFIG_HAS_SEGGER_RTT 1
#define CONFIG_NVS 1
#define CONFIG_NVS_LOG_LEVEL_DBG 1
#define CONFIG_NVS_LOG_LEVEL 4
#define CONFIG_LOG 1
#define CONFIG_LOG_OVERRIDE_LEVEL 0
#define CONFIG_LOG_MAX_LEVEL 4
#define CONFIG_LOG_FUNC_NAME_PREFIX_DBG 1
#define CONFIG_LOG_IMMEDIATE 1
#define CONFIG_LOG_DOMAIN_ID 0
#define CONFIG_LOG_BACKEND_UART 1
#define CONFIG_LOG_BACKEND_SHOW_COLOR 1
#define CONFIG_LOG_BACKEND_FORMAT_TIMESTAMP 1
#define CONFIG_NET_BUF 1
#define CONFIG_NET_BUF_USER_DATA_SIZE 1
#define CONFIG_NET_BUF_LOG_LEVEL_INF 1
#define CONFIG_NET_BUF_LOG_LEVEL 3
#define CONFIG_NETWORKING 1
#define CONFIG_NET_INIT_PRIO 90
#define CONFIG_NET_IF_MAX_IPV6_COUNT 1
#define CONFIG_NET_IF_UNICAST_IPV6_ADDR_COUNT 2
#define CONFIG_NET_IF_MCAST_IPV6_ADDR_COUNT 3
#define CONFIG_NET_IF_IPV6_PREFIX_COUNT 2
#define CONFIG_NET_INITIAL_HOP_LIMIT 64
#define CONFIG_NET_IPV6_MAX_NEIGHBORS 8
#define CONFIG_NET_IPV6_MLD 1
#define CONFIG_NET_IPV6_NBR_CACHE 1
#define CONFIG_NET_IPV6_ND 1
#define CONFIG_NET_IPV6_DAD 1
#define CONFIG_NET_IPV6_RA_RDNSS 1
#define CONFIG_NET_IPV6_LOG_LEVEL 0
#define CONFIG_NET_ICMPV6_LOG_LEVEL 0
#define CONFIG_NET_IPV6_NBR_CACHE_LOG_LEVEL 0
#define CONFIG_NET_TC_TX_COUNT 1
#define CONFIG_NET_TC_RX_COUNT 1
#define CONFIG_NET_TC_MAPPING_STRICT 1
#define CONFIG_NET_TX_DEFAULT_PRIORITY 1
#define CONFIG_NET_RX_DEFAULT_PRIORITY 0
#define CONFIG_NET_IP_ADDR_CHECK 1
#define CONFIG_NET_MAX_ROUTERS 1
#define CONFIG_NET_ROUTE 1
#define CONFIG_NET_MAX_ROUTES 8
#define CONFIG_NET_MAX_NEXTHOPS 8
#define CONFIG_NET_UDP 1
#define CONFIG_NET_UDP_CHECKSUM 1
#define CONFIG_NET_UDP_LOG_LEVEL 0
#define CONFIG_NET_MAX_CONN 4
#define CONFIG_NET_MAX_CONTEXTS 6
#define CONFIG_NET_CONTEXT_SYNC_RECV 1
#define CONFIG_NET_CONTEXT_CHECK 1
#define CONFIG_NET_PKT_RX_COUNT 4
#define CONFIG_NET_PKT_TX_COUNT 4
#define CONFIG_NET_BUF_RX_COUNT 16
#define CONFIG_NET_BUF_TX_COUNT 16
#define CONFIG_NET_BUF_FIXED_DATA_SIZE 1
#define CONFIG_NET_BUF_DATA_SIZE 64
#define CONFIG_NET_DEFAULT_IF_FIRST 1
#define CONFIG_NET_TX_STACK_SIZE 1200
#define CONFIG_NET_RX_STACK_SIZE 1500
#define CONFIG_NET_PKT_LOG_LEVEL 0
#define CONFIG_NET_DEBUG_NET_PKT_EXTERNALS 0
#define CONFIG_NET_CORE_LOG_LEVEL 0
#define CONFIG_NET_IF_LOG_LEVEL 0
#define CONFIG_NET_TC_LOG_LEVEL 0
#define CONFIG_NET_UTILS_LOG_LEVEL 0
#define CONFIG_NET_CONTEXT_LOG_LEVEL 0
#define CONFIG_NET_CONN_LOG_LEVEL 0
#define CONFIG_NET_ROUTE_LOG_LEVEL 0
#define CONFIG_NET_HTTP_LOG_LEVEL 0
#define CONFIG_NET_CONFIG_AUTO_INIT 1
#define CONFIG_NET_CONFIG_INIT_PRIO 95
#define CONFIG_NET_CONFIG_INIT_TIMEOUT 30
#define CONFIG_NET_CONFIG_LOG_LEVEL 0
#define CONFIG_NET_SOCKETS 1
#define CONFIG_NET_SOCKETS_POSIX_NAMES 1
#define CONFIG_NET_SOCKETS_POLL_MAX 3
#define CONFIG_NET_SOCKETS_CONNECT_TIMEOUT 3000
#define CONFIG_NET_SOCKETS_OFFLOAD 1
#define CONFIG_NET_SOCKETS_LOG_LEVEL 0
#define CONFIG_IMG_MANAGER 1
#define CONFIG_MCUBOOT_IMG_MANAGER 1
#define CONFIG_MCUBOOT_TRAILER_SWAP_TYPE 1
#define CONFIG_IMG_BLOCK_BUF_SIZE 512
#define CONFIG_IMG_ERASE_PROGRESSIVELY 1
#define CONFIG_IMG_MANAGER_LOG_LEVEL_INF 1
#define CONFIG_IMG_MANAGER_LOG_LEVEL 3
#define CONFIG_ENTROPY_DEVICE_RANDOM_GENERATOR 1
#define CONFIG_CSPRING_ENABLED 1
#define CONFIG_HARDWARE_DEVICE_CS_GENERATOR 1
#define CONFIG_FLASH_MAP 1
#define CONFIG_TEST_EXTRA_STACKSIZE 0
#define CONFIG_TEST_ARM_CORTEX_M 1
#define CONFIG_HAS_CMSIS_CORE 1
#define CONFIG_HAS_CMSIS_CORE_M 1
#define CONFIG_TOOLCHAIN_GNUARMEMB 1
#define CONFIG_LINKER_ORPHAN_SECTION_WARN 1
#define CONFIG_HAS_FLASH_LOAD_OFFSET 1
#define CONFIG_USE_DT_CODE_PARTITION 1
#define CONFIG_KERNEL_ENTRY "__start"
#define CONFIG_LINKER_SORT_BY_ALIGNMENT 1
#define CONFIG_SIZE_OPTIMIZATIONS 1
#define CONFIG_COMPILER_OPT ""
#define CONFIG_RUNTIME_ERROR_CHECKS 1
#define CONFIG_KERNEL_BIN_NAME "zephyr"
#define CONFIG_OUTPUT_STAT 1
#define CONFIG_OUTPUT_DISASSEMBLY 1
#define CONFIG_OUTPUT_PRINT_MEMORY_USAGE 1
#define CONFIG_BUILD_OUTPUT_BIN 1
#define CONFIG_BOOTLOADER_MCUBOOT 1
#define CONFIG_REBOOT 1
#define CONFIG_COMPAT_INCLUDES 1

RE: I2C communication problem with nRF9160

Simon — Thu, 23 Jul 2020 16:17:15 GMT

My suspicion is that when you enable I2C, both I2C instance 1 and 2 gets enabled and blocks access to UART1 and SPI2. Check the autoconf.h file generated in the build folder if this is the case.

Check the case below for an explanation on why you can't use the same instances of UART, SPI or I2C:

https://devzone.nordicsemi.com/support-private/support/251830

Best regards,

Simon

RE: I2C communication problem with nRF9160

duxinglang — Thu, 23 Jul 2020 03:52:14 GMT

the overlay file is this:

&spi2{
	compatible = "nordic,nrf-spim";
	status = "okay";
	sck-pin = <3>;
	mosi-pin = <4>;
	miso-pin = <5>;
};

&spi3{
	compatible = "nordic,nrf-spim";
	status = "okay";
	sck-pin = <22>;
	mosi-pin = <20>;
	miso-pin = <20>;
};

RE: I2C communication problem with nRF9160

duxinglang — Thu, 23 Jul 2020 03:51:26 GMT

And the dts file is like this:

/*
 * Copyright (c) 2018 Nordic Semiconductor ASA
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/ {
	model = "Nordic PCA10090 Dev Kit";
	compatible = "nordic,pca10090-dk", "nordic,nrf9160-sica",
		     "nordic,nrf9160";

	chosen {
		zephyr,console = &uart0;
		zephyr,shell-uart = &uart0;
		zephyr,uart-mcumgr = &uart0;
	};

	leds {
		compatible = "gpio-leds";
		led0: led_0 {
			gpios = <&gpio0 2 GPIO_INT_ACTIVE_HIGH>;
			label = "Green LED 0";
		};
		led1: led_1 {
			gpios = <&gpio0 3 GPIO_INT_ACTIVE_HIGH>;
			label = "Green LED 1";
		};
		led2: led_2 {
			gpios = <&gpio0 4 GPIO_INT_ACTIVE_HIGH>;
			label = "Green LED 2";
		};
		led3: led_3 {
			gpios = <&gpio0 5 GPIO_INT_ACTIVE_HIGH>;
			label = "Green LED 3";
		};
	};

	pwmleds {
		compatible = "pwm-leds";
		pwm_led0: pwm_led_0 {
			pwms = <&pwm0 2>;
		};
	};

	buttons {
		compatible = "gpio-keys";
		button0: button_0 {
			gpios = <&gpio0 8 GPIO_PUD_PULL_UP>;
			label = "Switch 1";
		};
		button1: button_1 {
			gpios = <&gpio0 9 GPIO_PUD_PULL_UP>;
			label = "Switch 2";
		};
		button2: button_2 {
			gpios = <&gpio0 6 GPIO_PUD_PULL_UP>;
			label = "Push button 1";
		};
		button3: button_3 {
			gpios = <&gpio0 7 GPIO_PUD_PULL_UP>;
			label = "Push button 2";
		};
	};

	/* These aliases are provided for compatibility with samples */
	aliases {
		led0 = &led0;
		led1 = &led1;
		led2 = &led2;
		led3 = &led3;
		pwm-led0 = &pwm_led0;
		sw0 = &button2;
		sw1 = &button3;
		sw2 = &button0;
		sw3 = &button1;
	};
};

&adc {
	status = "okay";
};

&gpiote {
	status = "okay";
};

&gpio0 {
	status = "okay";
};

&uart0 {
	status = "okay";
	current-speed = <115200>;
	tx-pin = <29>;
	rx-pin = <28>;
	rts-pin = <27>;
	cts-pin = <26>;
};

&uart1 {
	status = "okay";
	current-speed = <115200>;
	tx-pin = <31>;
	rx-pin = <30>;
	rts-pin = <14>;
	cts-pin = <15>;
};

&uart2 {
	tx-pin = <24>;
	rx-pin = <23>;
};

&i2c1 {
	compatible = "nordic,nrf-twim";
	status = "okay";
	sda-pin = <11>;
	scl-pin = <12>;
};

&i2c2 {
	compatible = "nordic,nrf-twim";
	status = "okay";
	sda-pin = <30>;
	scl-pin = <31>;
};

&pwm0 {
	status = "okay";
	ch0-pin = <2>;
};

&spi3 {
	compatible = "nordic,nrf-spim";
	status = "okay";
	sck-pin = <19>;
	mosi-pin = <18>;
	miso-pin = <17>;
};

&timer0 {
	status = "okay";
};

&timer1 {
	status = "okay";
};

&timer2 {
	status = "okay";
};

&flash0 {
	/*
	 * For more information, see:
	 * http://docs.zephyrproject.org/latest/guides/dts/index.html#flash-partitions
	 */
	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;

		boot_partition: partition@0 {
			label = "mcuboot";
			reg = <0x00000000 0x10000>;
		};
		slot0_partition: partition@10000 {
			label = "image-0";
		};
		slot0_ns_partition: partition@40000 {
			label = "image-0-nonsecure";
		};
		slot1_partition: partition@80000 {
			label = "image-1";
		};
		slot1_ns_partition: partition@b0000 {
			label = "image-1-nonsecure";
		};
		scratch_partition: partition@f0000 {
			label = "image-scratch";
			reg = <0x000f0000 0xa000>;
		};
		storage_partition: partition@fa000 {
			label = "storage";
			reg = <0x000fa000 0x00006000>;
		};
	};
};

/ {
	/* SRAM allocated and used by the BSD library */
	sram0_bsd: memory@20010000 {
		compatible = "mmio-sram";
	};

	/* SRAM allocated to the Non-Secure image */
	sram0_ns: memory@20020000 {
		compatible = "mmio-sram";
	};
};

/* Include partition configuration file */
#include "nrf9160_pca10090_partition_conf.dts"