Having trouble getting interrupts on the TX side

RE: Having trouble getting interrupts on the TX side

ovrebekk — Fri, 18 Sep 2020 11:54:49 GMT

Essentially you need to clear the interrupts every time they occur, to be ready to receive more interrupts.

It should work fine to clear the interrupts in the interrupt handler, like you describe.

If this is not working you need to scope the SPI lines to see if the communication looks OK.

Best regards
Torbjørn

RE: Having trouble getting interrupts on the TX side

morpho — Thu, 17 Sep 2020 21:10:02 GMT

I should be clearing the IRQs in the initialization stage, right? Currently I am disabling the respective interrupt that occurred inside the IRQ handler (i.e `TX_DS`, RX_DR)

RE: Having trouble getting interrupts on the TX side

ovrebekk — Fri, 04 Sep 2020 12:48:55 GMT

It sounds like you are not properly clearing the interrupt then.

A simple way to clear all the current interrupts is to write 0x70 to the STATUS register.

Are you doing this?

If you think you are doing it, but it still doesn't work, are you able to scope the SPI and IRQ lines and see what is going on on the bus?

Best regards
Torbjørn

RE: Having trouble getting interrupts on the TX side

morpho — Thu, 03 Sep 2020 15:12:24 GMT

Well the issue is subsequent interrupts don't occur after the first interrupt.

After reading the STATUS register, I still see `0x1E`.

Setting MAX RT: 0x0271e ----------- 0x01e00

Read Status register: 0x0700 ----------- 0x01e1e

RE: Having trouble getting interrupts on the TX side

ovrebekk — Mon, 24 Aug 2020 11:21:14 GMT

Do you see the IRQ pin go high again after you clear the MAX_RT bit?

Also, do you read back the STATUS register again to verify that the bit is cleared?

Best regards
Torbjørn

RE: Having trouble getting interrupts on the TX side

morpho — Fri, 21 Aug 2020 19:42:00 GMT

clearing the pending bit by writing 1 via `__HAL_GPIO_EXTI_CLEAR_IT`.

I see 0x1E as the status register's value so it's MAX_RT.

And yes I clear MAX_RT by setting the bit to 1.

RE: Having trouble getting interrupts on the TX side

ovrebekk — Mon, 17 Aug 2020 05:55:26 GMT

How do you clear the IRQ pin? By writing to the STATUS register?

Which interrupt are you getting? TX_DS or MAX_RT?

If you get the MAX_RT interrupt you might need to flush the TX FIFO before trying to send more data, unless you want to try to retransmit the same packet.

Best regards
Torbjørn

RE: Having trouble getting interrupts on the TX side

morpho — Fri, 14 Aug 2020 18:53:10 GMT

So I see when I restarted the program, I got the interrupt at the first attempt but then when I ran the program after, I didn't receive the interrupt. I'm clearing the IRQ pin in the ISR. What else could be the cause?

RE: Having trouble getting interrupts on the TX side

ovrebekk — Fri, 14 Aug 2020 12:28:42 GMT

I am trying to figure out if the issue could be hardware related, and get a better understanding of how you are controlling the nRF24L01+.

Assuming the interrupts are not disabled (which they don't seem to be based on your register readouts) there is no reason you shouldn't get some kind of interrupt after sending a packet, regardless of whether or not the packet is received by anyone.

Best regards
Torbjørn

RE: Having trouble getting interrupts on the TX side

morpho — Thu, 13 Aug 2020 14:36:29 GMT

I'm using an off the shelf nRF240l+ module.

I don't have a schematic per se and I don't mind sending you a capture of the setup itself; it's just a bit messy with all the wires. But what are you trying to figure out? Or perhaps what do you think may be wrong?

RE: Having trouble getting interrupts on the TX side

ovrebekk — Thu, 13 Aug 2020 08:57:06 GMT

I would basically like to get a bit more details about your hardware, if possible.

Have you made your own PCB with some MCU and the nRF24L01+, or are you using an off the shelf nRF24L01+ module?

If you have a schematic or a picture of a setup that could also be useful.

Best regards
Torbjørn

RE: Having trouble getting interrupts on the TX side

morpho — Wed, 12 Aug 2020 13:57:49 GMT

If the IRQ pin had gone lower, the interrupt would have occurred but I see it happen inconsistently.

it's a nRF24L01+ radio transceiver, and not sure what you mean by how is it being controlled. Could you elaborate?

i'm powering it at 3.3V.

RE: Having trouble getting interrupts on the TX side

ovrebekk — Wed, 12 Aug 2020 09:52:41 GMT

I mean if you measured the pin with a scope or logic analyzer to verify if it went low?

Can you give me a bit more information about the L01+ modules you are using, and what you are using to control them?

Also, what voltage level are you using?

Best regards
Torbjørn

RE: Having trouble getting interrupts on the TX side

morpho — Mon, 10 Aug 2020 22:30:06 GMT

CONFIG on the TX side has a value of `0x02`, which means `PWR_UP` is set.

And do you mean if the IRQ pin's PR bit is cleared?

And status register is 0x1E when I get an interrupt. But right now I am not getting one

RE: Having trouble getting interrupts on the TX side

ovrebekk — Mon, 10 Aug 2020 12:40:06 GMT

You should always get an interrupt on the TX side, whether or not the receiver is working.

If you have ACK enabled you will get the TX_DS interrupt when you receive an ACK, and if no ACK is received you should get the MAX_RT interrupt.

Can you confirm what the CONFIG register contains on the TX side?
Assuming the upper 4 bits are all 0 then all interrupts should be enabled.

A STATUS register value of 0x1E implies that the MAX_RT interrupt occurred, that is correct.

Have you checked the IRQ pin from your TX module manually to see if it is cleared or not?

Best regards
Torbjørn