nRF52840 - Understanding RAM AHB slaves and sections.

RE: nRF52840 - Understanding RAM AHB slaves and sections.

Nikosant03 — Thu, 20 Aug 2020 21:44:53 GMT

Could I re-open this thread?

RE: nRF52840 - Understanding RAM AHB slaves and sections.

Nikosant03 — Thu, 20 Aug 2020 12:45:45 GMT

Thank you for your support Einar!!

RE: nRF52840 - Understanding RAM AHB slaves and sections.

Einar Thorsrud — Thu, 20 Aug 2020 11:49:00 GMT

Hi,

Your understanding is correct.

RE: nRF52840 - Understanding RAM AHB slaves and sections.

Nikosant03 — Wed, 19 Aug 2020 13:44:18 GMT

Thank you for your effort Einar

[quote userid="7377" url="~/f/nordic-q-a/64907/nrf52840---understanding-ram-ahb-slaves-and-sections/265320"]So for section 0, bit in position 0 controls if the section is on or off in system ON mode, and bit in position 16 controls weather it is on of off in system OFF mode. For section 1 this would be bit positions 1 and 17 respectively.[/quote]

So, If I have understood correctly for AHB slave index 0-7 there are only two sections and the assosiated bit positions are 0,1,16,17 while for AHB slave index 8 there are six sections and the assosiated bit positions are 0,1,2,3,4,5,16,17,18,19,20,21 right?

So, actually the bits 6-15 & 22-31 of RAM[n].POWER register have no affect and I won't need them anywhere right?

RE: nRF52840 - Understanding RAM AHB slaves and sections.

Einar Thorsrud — Wed, 19 Aug 2020 12:36:45 GMT

Hi Nick,

[quote user="Nikosant03"]1. Section 0 & Section 1 of RAM1 which field (S[i]) within POWER register represent?[/quote]

This is unfortunately not clearly documented in the PS, but you can refer to the components\device\nrf52840_bitfields.h file to see this. There you can see a some relevant defines for this question:

/* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */
#define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
#define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
#define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
#define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */

/* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */
#define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
#define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
#define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
#define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */

...

/* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */
#define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
#define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
#define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
#define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */

/* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */
#define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
#define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
#define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
#define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */

So for section 0, bit in position 0 controls if the section is on or off in system ON mode, and bit in position 16 controls weather it is on of off in system OFF mode. For section 1 this would be bit positions 1 and 17 respectively.

[quote user="Nikosant03"]2. Using the s140 API for RAM retention, is the snippet below correct in order to put RAM2 AHB slave section 0 in retention?[/quote]

No. The AHB slave index is correct, but you are referring to section 2 in this case (which does not exist), as you use POWER_RAM_POWER_S2RETENTION_Pos (and POWER_RAM_POWER_S2RETENTION_On, though that does not really matter as it is just 1 in any case). You should have used POWER_RAM_POWER_S0RETENTION_On and POWER_RAM_POWER_S0RETENTION_Pos. Other than that it is correct.

Br,

Einar

RE: nRF52840 - Understanding RAM AHB slaves and sections.

Nikosant03 — Tue, 18 Aug 2020 13:20:07 GMT

Thank you for your answer Einar

[quote userid="7377" url="~/f/nordic-q-a/64907/nrf52840---understanding-ram-ahb-slaves-and-sections/265090"]And the section (S) field within each POWER register instance represents a section within that slave[/quote]

How does it represented? For example, n=0 represents RAM0 and looking the RAM layout I see that RAM0 has two sections (Section 0 & Section 1) but the section (S) field within each POWER register instance could be 0-15 (it shouldn't be 0-1?)

1. Section 0 & Section 1 of RAM1 which field (S[i]) within POWER register represent?

2. Using the s140 API for RAM retention, is the snippet below correct in order to put RAM2 AHB slave section 0 in retention?

#define RAM_AHB_slave 2

ret_code_t err_code;
err_code = sd_power_ram_power_set(RAM_AHB_slave, POWER_RAM_POWER_S2RETENTION_On << POWER_RAM_POWER_S2RETENTION_Pos);
APP_ERROR_CHECK(err_code);

RE: nRF52840 - Understanding RAM AHB slaves and sections.

Einar Thorsrud — Tue, 18 Aug 2020 12:23:11 GMT

Hi Nick,

It is not easy to see from the product specification, but each instance of the RAM[n].POWER register represents an AHB slave (n = 0, represents RAM0, n = 1, represents RAM1, ...). And the section (S) field within each POWER register instance represents a section within that slave. You can refer to this post to see a code snippet that powers down all sections.

Einar