RE: Duty Cycle, Sequence Values, and Top Value Relationship to achieve 50% duty cycle

matty — Thu, 20 Aug 2020 11:19:01 GMT

Thank you haakonsh.

Question 3 - I missed the Connector Interface section for the nRF52840 DK. I've got to open my eyes.

Question 2 - I am working on your 2nd suggestion and think it will do the job. I'll definitely check out your first suggestion.

Question 1 - This all originated from Devzone case ID's: 115712, 114746, 112874, 235644, etc. I'm using the same Knowles microphone and need 24bit data from a 1 to 4 MHz SCK. I think the only solution is to use the PWM Driver to supply the SCK and WS/LRCK to the I2S Peripheral setup in Slave Mode. Decoding the I2S Peripheral's output will be another challenge.

"You've measured a difference in time of two full periods, not a peak and a trough. " That was a key observation for me, I didn't understand that control of the PWM, (top value / sequence value), was an entire period for the PWM. Putting these PWM outputs together produces a "square wave" with a given period. It is beginning to make sense to me now.

Thanks again for your fast response.

RE: Duty Cycle, Sequence Values, and Top Value Relationship to achieve 50% duty cycle

haakonsh — Thu, 20 Aug 2020 08:11:36 GMT

Why can't you generate the MCK with the I2S peripheral?

I think you can use just one PWM for both your outputs if you intend to use the same PWM frequency for both outputs.

[quote user=""]Question 1: How do you use .top_value and nrf_pwm_values_common_t seq_values[] to produce a 50% duty cycle? [/quote]

The nrf_pwm_values_common_t is an array of uint16_t, so I think it's just the raw compare value of the timer. Ie. half your COUNTERTOP value for 50% duty-cycle.

[quote user=""][/quote]

I've figured out that for a 50% duty cycle, sequence has to be 1/2 of top value but when you look at these two screen shots you can see that the peak and the trough have different widths. Is that to be expected and is it unavoidable?

That's not what your scope show. You've measured a difference in time of two full periods, not a peak and a trough. What you have shown is that there is a variance in the PWM frequency, which could be due to either capacitive loading or an inaccurate clock. IF the HFCLK is running from the internal 64MHz RC oscillator then there is usually some jitter, but I think a more likely culprit is capacitive loading. The Saleae probes are ~10pF and the pin is 3pF, if there's other stuff connected then the capacitance increases further. I suggest you start the HFXO and see if that helps, if it does not then it's definitely due to capacitive loading.

[quote user=""]Question 2: Is there anyway of starting two separate nrfx_pwm_config_t instances simultaneously?[/quote]

You can use the EGU to generate an event and connect it to the TASKS_SEQSTART[n] task of both PWM instances (you need to 'fork' the event).

[quote user=""]If I wanted my 2nd channel to have a duty cycle that was 32x's larger than my first channel, how would I put the sequence array together?[/quote]

Do they still share the same PWM frequency (COUNTERTOP)? If so the sequence value must be 32x larger.

[quote user=""]Question 3: Is there any reason GPIO pins 0.00 through 0.10 wouldn't be available for use by the PWM Driver?[/quote]

See Connector interface