RE: number of I/Q samples and the sampling offset

tc_2020 — Fri, 04 Sep 2020 14:26:55 GMT

Hi Dmitry, Thanks for your quick response!

Just read the white paper you provided, so for the 1-us gap, I think it's explained in section 3.2 First IQ samples. According to Figure 11 in the white paper, the gap is the TSAMPLESPACINGREF + TSWITCHSPACING/2 = 1.125 to my case.

If this is true, and according to your answer of my first question, why the total sampling number is still 160, rather than 160-8 (8 samples in the first switch slot).

RE: number of I/Q samples and the sampling offset

Dmitry — Fri, 04 Sep 2020 13:22:05 GMT

Hi,

[quote userid="89493" url="~/f/nordic-q-a/65581/number-of-i-q-samples-and-the-sampling-offset"]This means the sampling is not only happening during sampling slot, but both the switch slot and sampling slot. Is this what chip is doing?[/quote]

Yes, that's true.

[quote userid="89493" url="~/f/nordic-q-a/65581/number-of-i-q-samples-and-the-sampling-offset"]You can see there is a disconnection from 12us when the reference period ends. Is this the sample offset indicated in the production specification?[/quote]

There is an 1-us gap after reference period, it's not related to sampling offset. The documentation is not clear about this point, but there is a white paper with better description.

You don't need to figure out an exact times at this moment. When you'll have a prototype hardware, take a measurement at 0.125us rate and you will see the best sampling point for your array and switch IC.