How fast can the counter count?

RE: How fast can the counter count?

DBT — Mon, 21 Sep 2020 16:18:37 GMT

This looks like the answer to my original question, but with the fix for errata 155 in place I was able to use a clock speed of 3.072MHz at 50% duty cycle - slightly higher than the 2.67MHz proposed here.

RE: How fast can the counter count?

DBT — Mon, 21 Sep 2020 16:17:13 GMT

This seemed to fix it! Now CSN goes high after 10 clocks

RE: How fast can the counter count?

hmolesworth — Mon, 21 Sep 2020 15:54:52 GMT

Did you try the workaround for errata 155? IN event may occur more than once on input edge that was nRF52832, same errata on nRF52840 here

RE: How fast can the counter count?

Dmitry — Mon, 21 Sep 2020 15:23:41 GMT

Hi,

it seems I2S-CLK is really too fast for GPIOTE. In this thread, Martin suggests no more than 2.67MHz for 50%-duty signal.

RE: How fast can the counter count?

DBT — Mon, 21 Sep 2020 15:12:05 GMT

By the way, I tested at half speed (I2S-CLK set to 1.536MHz instead of 3.072MHz) and that seemed to work. The CSN pin goes high after 10 clock cycles.

Isn't this much slower than expected? I would think from your initial response that the GPIOTE/PPI circuits should be able to handle signals up to 8MHz or so.

RE: How fast can the counter count?

DBT — Mon, 21 Sep 2020 14:10:38 GMT

Using a separate pin for low-to-high transition did not fix it.

The green trace is this new pin (SPI_CSN2_PIN). There are still 17 clocks instead of 10 between CSN going low and CSN2 going high

Here's the new source code

devzone.nordicsemi.com/.../7455.main.c

What do you think the race condition may be?

RE: How fast can the counter count?

haakonsh — Mon, 21 Sep 2020 08:43:45 GMT

Thank you for the detailed explanation, I think I understand what the issue is now.

There might be a race condition somewhere.

I suggest you map the SPI-CSN transition from low to high to a separate GPIO pin and see if it will trigger the transition correctly, I'm curious to see what happens when there's only one GPIOTE channel controlling the pin during this transition.

RE: How fast can the counter count?

DBT — Fri, 18 Sep 2020 14:29:20 GMT

I looked through the errata on the processor in the PDK board and didn't see a problem, but I'm getting a DK board just to be sure.

Sorry, I probably gave too much detail and it's confusing you.

I'm not using the I2S or SPI peripherals on the nRF52840 at all.

The I2S is coming from an Audio ADC chip and has 8 channels of audio, so it uses TDM.

The SPI bus is going to an nRF5340 (we had to use SPI because the I2S peripheral on the nRF5340 only supports stereo audio - not 8 channels)

I'm only using GPIOTE, PPI and TIMER0 on the nRF52840.

The nRF53840 is between the Audio ADC and the nRF5340.

You can ignore the fact that its implementing an I2S to SPI converter.

Here's the source code

devzone.nordicsemi.com/.../6724.main.c

Here's an oscilloscope trace

Once SPI-CSN goes low, I want it to go high again after 10 clocks of I2S-CLK (10 is just a number I chose for test - The actual implementation will use 128 clocks)

It doesn't actually go high until after 18-19 clocks, depending on whether you count the one that occurs at the same time that SPI-CSN is going low. And its not always the same number - sometimes is 16 and other times 20.

RE: How fast can the counter count?

haakonsh — Fri, 18 Sep 2020 08:58:02 GMT

The preview DK likely has a few erratas, you really need to get a newer DK.

Do you have a scope of the SPI and I2S communication?

The GPIOTE tasks should only be delayed by one 16MHz clock cycle, 62.5ns. There is however some delay in the GPIO peripheral, but that should be much lower than one 16MHz clock cycle.

[quote user=""][/quote]

So it takes the I2S FS (frame sync) and CLK (clock) signals as inputs and generates the SPI CSN (chip select) signal

Then the I2S clock and data signals pass through unmodified to the SPI bus clock and data signals.

Have I understood you correctly that the nRF52 operates as an I2S slave and a SPI master?

[quote user=""]Then the I2S clock and data signals pass through unmodified to the SPI bus clock and data signals.[/quote]

Can you elaborate?
Do you mean that you share the DMA buffer between the I2S and SPI peripheral?