Setting write latch of MT25Q SPI flash?

RE: Setting write latch of MT25Q SPI flash?

turboscrew — Thu, 15 Oct 2020 15:32:59 GMT

As you can see, everything about the transfers are globals.

Anyway, you might want to bring that to the developers, but I got this problem solved, so this issue can be closed.

RE: Setting write latch of MT25Q SPI flash?

turboscrew — Thu, 15 Oct 2020 15:30:36 GMT

Unfortunately, I don't have the time. I have to get this demo working, and the deadline is approaching.

RE: Setting write latch of MT25Q SPI flash?

Kenneth — Thu, 15 Oct 2020 14:45:12 GMT

I don't have a good explanation to the inconsistency, it may be a variable that is not persistent (maybe optimized away if not static, while still pointed to in memory by the spi manager), I suggest to try the spi driver directly (\examples\peripheral\spi) instead of the spi manager.

Best regards,
Kenneth

RE: Setting write latch of MT25Q SPI flash?

turboscrew — Thu, 15 Oct 2020 13:12:03 GMT

Extra. It seems like it comes from receive buffer size 1. Then again, why is it there in the first time, but not in the second time? And some chips send the current status as response to the command byte. Catching that should also be achievable?

RE: Setting write latch of MT25Q SPI flash?

Kenneth — Thu, 15 Oct 2020 12:57:11 GMT

Can you use the spi driver directly instead of the spi manager? You may refer to \examples\peripheral\spi for example.

Regarding the ???, is that byte wrong (should not be FF) or is it an extra byte that should not be there (wrong length of transfer).

Best regards,
Kenneth

RE: Setting write latch of MT25Q SPI flash?

turboscrew — Thu, 15 Oct 2020 12:34:26 GMT

Now I saw something:

MOSI 66, MISO FF // reset enable

MOSI FF, MISO FF // ???

MOSI 99, MISO FF // reset memory

MOSI 05, MISO FF // read status

MOSI FF, MISO 02 // status value

MOSI 70, MISO FF // read flag status

MOSI FF, MISO 80 // flag status value

MOSI 06, MISO FF // write enable

MOSI FF, MISO FF // ???

MOSI 06, MISO FF // write enable

MOSI 05, MISO FF // read status

MOSI FF, MISO 02 // status value

MOSI 70, MISO FF // read flag status

MOSI FF, MISO 80 // flag status value

Looks like the extra MOSI FF, MISO FF causes the problem.

Where does that extra FF-write come from? And why it's there sometimes, but not always?

RE: Setting write latch of MT25Q SPI flash?

Kenneth — Tue, 13 Oct 2020 13:01:18 GMT

I suggest to wait for the logic analyzer and compare with and without the #if statement.

Best regards,
Kenneth

RE: Setting write latch of MT25Q SPI flash?

turboscrew — Tue, 13 Oct 2020 11:56:02 GMT

Checked the extflash_transact_done reset and added som more just in case.

No change.

RE: Setting write latch of MT25Q SPI flash?

turboscrew — Tue, 13 Oct 2020 11:25:06 GMT

I agree, but I can't get any until, maybe, Thursday.

RE: Setting write latch of MT25Q SPI flash?

Kenneth — Tue, 13 Oct 2020 11:23:33 GMT

To debug I think getting a logic analyzer (e.g. https://www.saleae.com/) trace would be very useful.

Maybe double check that extflash_transact_done is reset before each transfer.

Best regards,
Kenneth

RE: Setting write latch of MT25Q SPI flash?

turboscrew — Tue, 13 Oct 2020 10:48:30 GMT

And reading the chip ID bytes (20 bytes) hasn't caused any problems.