QSPI erase/write handling

RE: QSPI erase/write handling

MKJ — Thu, 26 Nov 2020 16:54:23 GMT

Yes, that's fine - please close the issue

RE: QSPI erase/write handling

ovrebekk — Thu, 26 Nov 2020 15:12:46 GMT

You welcome, I will consider the case closed then if you don't have more questions.

RE: QSPI erase/write handling

MKJ — Wed, 25 Nov 2020 14:05:05 GMT

Thanks, as long as there is a rational answer

RE: QSPI erase/write handling

ovrebekk — Wed, 25 Nov 2020 11:27:22 GMT

Hi Martin

The unused bits in the registers could be used for internal status information, so they are not necessarily guaranteed to be 0 at all times.

I double checked with the designers, and they ensured me that the fields listed in the product specification (such as the READY bit) are all in the right places. 🙂

Best regards
Torbjørn

RE: QSPI erase/write handling

MKJ — Tue, 24 Nov 2020 14:29:29 GMT

Torbjorn,

Thanks. When I read the QSPI STATUS register with the debugger I get, in hex, the following:

40029604 0A 00 00 42

The bottom byte has bit 3 set (QSPI Ready) but also has bit 1 set.

The upper byte (42) reflects the memory chip's status register which I validated independently as correct.

We get the same result if we read the STATUS register without the debugger.

Martin

RE: QSPI erase/write handling

ovrebekk — Tue, 24 Nov 2020 13:41:48 GMT

[quote user="MKJ"]A related question is when is the status register of the external memory read into the top byte of the QSPI STATUS register? Is it updated periodically or only after read/write/erase?[/quote]

As mentioned earlier this is read automatically before starting a write/read/erase operation, to ensure that the flash device is ready to accept new commands.

[quote user="MKJ"]Also is the datasheet correct for the STATUS register - I see bit 1 set to '1'[/quote]

You mean you see bit 1 set to 1 in the debugger?

Best regards
Torbjørn

RE: QSPI erase/write handling

ovrebekk — Tue, 24 Nov 2020 13:33:55 GMT

Hi Martin

[quote user=""]1) If I immediately issue a QSPI Write command then does the chip wait until the external QSPI chip has finished the erase?[/quote]

At the start of every command the QSPI interface will automatically read the status register, to make sure it doesn't read or write unless the device is idle.

[quote user=""]2) If it does wait then is there a timeout on this or will it hang forever?[/quote]

The QSPI should retry forever, yes. There is no defined timeout.

Best regards
Torbjørn

RE: QSPI erase/write handling

MKJ — Mon, 23 Nov 2020 16:39:40 GMT

Also is the datasheet correct for the STATUS register - I see bit 1 set to '1'

RE: QSPI erase/write handling

MKJ — Mon, 23 Nov 2020 11:01:14 GMT

A related question is when is the status register of the external memory read into the top byte of the QSPI STATUS register? Is it updated periodically or only after read/write/erase?