Power off state of nRF51822 GPIOs

RE: Power off state of nRF51822 GPIOs

Sourabh Barve — Mon, 08 Aug 2016 09:05:50 GMT

Is this same in case of nrf52?

RE: Power off state of nRF51822 GPIOs

Ole Morten — Thu, 24 Oct 2013 09:14:51 GMT

No problem, but I'd be happy if you could sign in and accept the answer if you found it useful! :-)

RE: Power off state of nRF51822 GPIOs

Guest — Mon, 21 Oct 2013 15:13:18 GMT

This makes sense. I'm implementing a totally-off-mode for shipping and storage. Thanks for the detailed response!

RE: Power off state of nRF51822 GPIOs

Bastiaan — Mon, 21 Oct 2013 15:13:18 GMT

This makes sense. I'm implementing a totally-off-mode for shipping and storage. Thanks for the detailed response!

RE: Power off state of nRF51822 GPIOs

Ole Morten — Mon, 21 Oct 2013 09:38:58 GMT

That the GPIO configuration registers are retained means that the configuration is kept through reset, as shown in the table in section 11.1.7.8 in the nRF51 Reference Manual. It does not mean that the configuration is kept when the device does not have power, since at that point, all data not written to flash is lost. Only the registers in FICR and UICR are flash registers, not the GPIO ones.

Therefore, if you completely remove power from the nRF51, all pins should be considered floating, and you should be careful not to apply any voltage to them. Doing so would be outside the "Absolute maximum ratings" for the chip, which states that any voltage above VDD + 0.3 V is too much, and in this case, VDD is 0. (In practice you are not likely to destroy the chip, but still.) Pulling a GPIO high when the power is off may actually result in the chip trying to run, which is most often undesirable.

If the sub-1 µA current the chip draws in system off isn't extremely important to you, it will therefore in most cases be much easier to just put the chip in system off instead of removing power. In system off, all GPIOs will keep their defined state.