52840 QIAA DC/DC ref layout and cap selection

RE: 52840 QIAA DC/DC ref layout and cap selection

ketiljo — Tue, 08 Dec 2020 09:44:32 GMT

You may see excessive spurious around the carrier if the 1 µF cap is placed near the DEC6 pin (E24). It must be close to the DEC4 pin (B5). Use the values in the reference schematic and make sure the placement in the schematic is correct for the layout as well.

RE: 52840 QIAA DC/DC ref layout and cap selection

Namklak — Mon, 07 Dec 2020 17:05:45 GMT

Good info. And close check of the spec sheet reveals the 47nF we are using does turn into an inductor at 50MHz as oppose to 12MHz of the 1uF - and also dips to a lower impedance of 10mOhms, compared to 30mOhns of the 1uF.

Something I didn't mention is when running the LDO with potentially a combo of bad layout and wrong caps, the LDO broke into oscillation at 12MHz. So with our new board, with LDO on, we saw a 12MHz sideband on the 2.4G, and with DC/DC we saw an 8MHz sideband. I think the DC/DC caused 8MHz sideband is explained by the switching freq of the DC/DC.

Do you have any comments on loading of the LDO to keep it stable?

On our board (we are going to change the layout) just using 1uF everywhere "fixed" the problem, but we'd like to know the LDO stability answer while we redesign our board.

Thanks.

RE: 52840 QIAA DC/DC ref layout and cap selection

ketiljo — Mon, 07 Dec 2020 14:21:18 GMT

The reason for the smaller cap in parallel with the large cap is that the HF properties of the large cap isn't good enough to filter the harmonics of the DCDC converter good enough. The receiver sensitivity will be affected at some channels without this.

It's true that modern ceramic caps have a lower ESR, but it's still not enough. If you want to omit the small cap, you can always do so, but you should measure sensitivity on all channels to be sure it's not affected.