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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>NRF51822 layout - do we need Cu-carve-out on layer 2 and 3?</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/6921/nrf51822-layout---do-we-need-cu-carve-out-on-layer-2-and-3</link><description>Hi! 
 I have reviewed the NRF518 reference design, i.e., case &amp;quot;PCB layout recommendations for the NRF51822 WLCSP62 package&amp;quot; and the layout pdf files provided therein: 
 nrf51822_ceaa_1v8_pcb.pdf 
 I am puzzled about the Cu-carve-out on layer 2 and</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Thu, 28 May 2015 09:23:43 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/6921/nrf51822-layout---do-we-need-cu-carve-out-on-layer-2-and-3" /><item><title>RE: NRF51822 layout - do we need Cu-carve-out on layer 2 and 3?</title><link>https://devzone.nordicsemi.com/thread/24411?ContentTypeID=1</link><pubDate>Thu, 28 May 2015 09:23:43 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:ef96e1f2-2a07-4194-89af-00fdf8114d90</guid><dc:creator>Carl Fredrik Leanderson</dc:creator><description>&lt;p&gt;Hi Fredrik!&lt;/p&gt;
&lt;p&gt;Thank you very much for the update! This answers my question. Please close the case.&lt;/p&gt;
&lt;p&gt;Kind regards&lt;/p&gt;
&lt;p&gt;/CF&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: NRF51822 layout - do we need Cu-carve-out on layer 2 and 3?</title><link>https://devzone.nordicsemi.com/thread/24410?ContentTypeID=1</link><pubDate>Thu, 07 May 2015 11:27:30 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:b2c9fe3f-70cd-4802-a275-7f6a9e98a4fc</guid><dc:creator>Fredrik Sundt Brynhildsvoll</dc:creator><description>&lt;p&gt;Hi,
the area you are referring to is below the matching circuit of the antenna.
This is a keep-out area, and it is there to minimize the stray capacitance between the matching circuit and the rest of the layout.
If you use this area (e.g. route in it) there will be (more) stray capacitance which &lt;strong&gt;will influence the RF performance&lt;/strong&gt;. How the performance is influenced depends on many factors (the performance can be simulated, but it takes a lot of time and it is costly).&lt;/p&gt;
&lt;p&gt;So it is not a good idea to use this area. But if you really need to route under the nRF51822 you should keep as far away from the matching circuit as possible. (Keep as far right ass possible in the layout).&lt;/p&gt;
&lt;p&gt;In the nRF51822 &lt;a href="https://www.nordicsemi.com/eng/nordic/Products/nRF51822/nRF51822-PS/20339"&gt;product specification&lt;/a&gt;  (chapter 11) you can read about PCB guidelines. I would recommend following these guidelines. This way you can avoid a lot of problems in your design.&lt;/p&gt;
&lt;p&gt;I hope this answers your question.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>