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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Single layer 3/3 mil fanout of the inner row of aQFN package?</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/69353/single-layer-3-3-mil-fanout-of-the-inner-row-of-aqfn-package</link><description>I am designing a PCB for the nRF52833 aQFN chip. To reduce the cost of the PCB I would like to fanout the inner row of the IC package on a single layer by using 3/3mil traces, instead of using via in pad technology. According to my calculations this should</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Fri, 11 Dec 2020 10:59:07 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/69353/single-layer-3-3-mil-fanout-of-the-inner-row-of-aqfn-package" /><item><title>RE: Single layer 3/3 mil fanout of the inner row of aQFN package?</title><link>https://devzone.nordicsemi.com/thread/284488?ContentTypeID=1</link><pubDate>Fri, 11 Dec 2020 10:59:07 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:b59e8d5e-42c5-4627-b208-213f2175df57</guid><dc:creator>ketiljo</dc:creator><description>&lt;p&gt;Sounds hard to do. You must check with your PCB supplier if that&amp;#39;s ok or not.&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>