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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Testing 48MHz QSPI and switching modes on QSPI chip requiring 2 clock rates in zephyr (nRF connect SDK)</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/70175/testing-48mhz-qspi-and-switching-modes-on-qspi-chip-requiring-2-clock-rates-in-zephyr-nrf-connect-sdk</link><description>We are using an MX25R6435FZNIL0 part on a design with a nRF5340 module and wish to test that 48MHz operation of QSPI is working, we are using the latest master version of the nRF connect SDK. However, it seems that the part we, despite supporting 80MHz</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Thu, 07 Jan 2021 11:35:56 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/70175/testing-48mhz-qspi-and-switching-modes-on-qspi-chip-requiring-2-clock-rates-in-zephyr-nrf-connect-sdk" /><item><title>RE: Testing 48MHz QSPI and switching modes on QSPI chip requiring 2 clock rates in zephyr (nRF connect SDK)</title><link>https://devzone.nordicsemi.com/thread/287930?ContentTypeID=1</link><pubDate>Thu, 07 Jan 2021 11:35:56 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:a9c093a7-3fef-492c-918b-82d26d96ae82</guid><dc:creator>H&amp;#229;kon Alseth</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;The qspi module in zephyr sets the ifconfig1 once on init:&lt;/p&gt;
&lt;p&gt;&lt;a href="https://github.com/nrfconnect/sdk-zephyr/blob/master/drivers/flash/nrf_qspi_nor.c#L368"&gt;https://github.com/nrfconnect/sdk-zephyr/blob/master/drivers/flash/nrf_qspi_nor.c#L368&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;And there doesn&amp;#39;t look like there&amp;#39;s any API for dynamically changing this. You could run uninit (&lt;a href="https://github.com/NordicSemiconductor/nrfx/blob/master/drivers/src/nrfx_qspi.c#L324"&gt;https://github.com/NordicSemiconductor/nrfx/blob/master/drivers/src/nrfx_qspi.c#L324&lt;/a&gt;) and init the module again with a new clock freq.&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
[quote user=""]and we might also need to add in some dummy clock cycle support - how do we go about doing this? It doesn&amp;#39;t seem like Zephyr RTOS is designed around being able to cater for such a scenario.[/quote]
&lt;p&gt;&amp;nbsp;You can set the clock delay in IFCONFIG1 register:&amp;nbsp;&lt;a href="https://infocenter.nordicsemi.com/topic/ps_nrf5340/qspi.html?cp=3_0_0_6_24_10_49#register.IFCONFIG1"&gt;https://infocenter.nordicsemi.com/topic/ps_nrf5340/qspi.html?cp=3_0_0_6_24_10_49#register.IFCONFIG1&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;Have you looked at the QSPI hardware interface description and checked if this is sufficient towards the mode you&amp;#39;re hoping to use? dummy data is being sent in some specific read modes:&lt;/p&gt;
&lt;p&gt;&lt;a href="https://infocenter.nordicsemi.com/topic/ps_nrf5340/qspi.html?cp=3_0_0_6_24_9#interface_description"&gt;https://infocenter.nordicsemi.com/topic/ps_nrf5340/qspi.html?cp=3_0_0_6_24_9#interface_description&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Kind regards,&lt;/p&gt;
&lt;p&gt;Håkon&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>