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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>The status of USB signal pin D+/D-  when USBD is disable</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/70588/the-status-of-usb-signal-pin-d-d--when-usbd-is-disable</link><description>Hello Devzone 
 
 Currently, we have below USBD application scenario 
 now the user are using the nrf52820 with disable the USB p eripheral and they have another USB IC connects to the USB bus. 
 in the future, they may disable the USB IC and use nrf52820</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Mon, 18 Jan 2021 16:07:12 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/70588/the-status-of-usb-signal-pin-d-d--when-usbd-is-disable" /><item><title>RE: The status of USB signal pin D+/D-  when USBD is disable</title><link>https://devzone.nordicsemi.com/thread/289843?ContentTypeID=1</link><pubDate>Mon, 18 Jan 2021 16:07:12 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:d632c859-b7fc-45a3-9c9a-ceb03f6cd8ae</guid><dc:creator>ovrebekk</dc:creator><description>&lt;p&gt;Hi David&lt;/p&gt;
&lt;p&gt;1. Apparently there is a parasitic coupling between the D+ and D- lines and ground when the USBD peripheral is disabled, since the D+ and D- lines are connected to the DECUSB line by ESD diodes, and DECUSB gets pulled to ground when USBD is disabled.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Exactly what impact this has on the impedance is not specified. I will try to find some more specific information about this and get back to you.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;2. Even if the impedance of the D+ and D- pads on the chip is high you will inevitably get some stray capacitance from such a configuration, and I am not sure you will be able to pass USB certification. This is not a configuration that USB was designed to support, and even with the relatively low clock speed of full speed USB you might have issues trying to certify such a design.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;In other words it&amp;#39;s not something I would recommend if you can find some alternative way to configure your design, such as using a different interface between the nRF chip and the USB IC.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Best regards&lt;br /&gt;Torbjørn&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>