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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>SPI Slave cannot receive data, sending data to master normally</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/70641/spi-slave-cannot-receive-data-sending-data-to-master-normally</link><description>Hi all, 
 
 I am using a custom board with NRF 52840 with SDK15.2 as slave and STM as master. I cannot receive right data, but the data to STM is right. 
 
 The above are the setup, and the following are the part that prepare buffer. 
 
 What I got from</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Wed, 16 Feb 2022 09:55:15 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/70641/spi-slave-cannot-receive-data-sending-data-to-master-normally" /><item><title>RE: SPI Slave cannot receive data, sending data to master normally</title><link>https://devzone.nordicsemi.com/thread/353309?ContentTypeID=1</link><pubDate>Wed, 16 Feb 2022 09:55:15 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:45932687-510b-4543-8a16-8d8c8d59784a</guid><dc:creator>ankushn_14</dc:creator><description>&lt;p&gt;Hi Marco, How are you doing?&lt;/p&gt;
&lt;p&gt;I am facing the similar issue like you. Were you able to resolve yours?&lt;/p&gt;
&lt;p&gt;Below is my code. I am sending 128 bytes of the data and receiving 128 back. I checked from the oscilloscope. Master is sending right data at 1 MHz frequency. But the slave is not receiving. Event_Handler is getting called successfully but the rx buffer is 0 always. Below is my code. It would be really nice if you can help me here.&lt;/p&gt;
&lt;p&gt;#include &amp;quot;sdk_config.h&amp;quot;&lt;br /&gt;#include &amp;quot;nrf_drv_spis.h&amp;quot;&lt;br /&gt;#include &amp;quot;nrf_gpio.h&amp;quot;&lt;br /&gt;#include &amp;quot;boards.h&amp;quot;&lt;br /&gt;#include &amp;quot;app_error.h&amp;quot;&lt;br /&gt;#include &amp;lt;string.h&amp;gt;&lt;/p&gt;
&lt;p&gt;#include &amp;quot;nrf_log.h&amp;quot;&lt;br /&gt;#include &amp;quot;nrf_log_ctrl.h&amp;quot;&lt;br /&gt;#include &amp;quot;nrf_log_default_backends.h&amp;quot;&lt;/p&gt;
&lt;p&gt;#define SPIIF_HW_SYNC_START (0xAABBu)&amp;nbsp;&lt;br /&gt;#define SPIIF_HW_SYNC_END (0x55CCu)&lt;br /&gt; &lt;br /&gt;#define SPI_BLOCK_SIZE (118u)&lt;/p&gt;
&lt;p&gt;typedef struct&lt;br /&gt;{&lt;br /&gt; uint8_t dummy;&amp;nbsp;&lt;br /&gt;uint8_t sequenceCnt;&lt;br /&gt; uint16_t dataLen;&lt;br /&gt; uint16_t syncStart;&lt;br /&gt; uint8_t dataBuffer[SPI_BLOCK_SIZE];&amp;nbsp;&lt;br /&gt; uint16_t syncEnd&lt;br /&gt; uint16_t dataCrc16;&amp;nbsp;&lt;br /&gt;} SPIIF_SPI_PACKET_T;&lt;/p&gt;
&lt;p&gt;&lt;br /&gt;SPIIF_SPI_PACKET_T gSpiIfSpiTx __attribute__((aligned(32)));&lt;/p&gt;
&lt;p&gt;#define SPIS_INSTANCE 1 /**&amp;lt; SPIS instance index. */&lt;br /&gt;static const nrf_drv_spis_t spis = NRF_DRV_SPIS_INSTANCE(SPIS_INSTANCE);/**&amp;lt; SPIS instance. */&lt;/p&gt;
&lt;p&gt;static uint8_t m_tx_buf[sizeof(SPIIF_SPI_PACKET_T)]; /**&amp;lt; TX buffer. */&lt;br /&gt;static uint8_t m_rx_buf[sizeof(SPIIF_SPI_PACKET_T)]; /**&amp;lt; RX buffer. */&lt;br /&gt;static const uint8_t m_length = sizeof(SPIIF_SPI_PACKET_T); /**&amp;lt; Transfer length. */&lt;/p&gt;
&lt;p&gt;static volatile bool spis_xfer_done; /**&amp;lt; Flag used to indicate that SPIS instance completed the transfer. */&lt;/p&gt;
&lt;p&gt;/**&lt;br /&gt; * @brief SPIS user event handler.&lt;br /&gt; *&lt;br /&gt; * @param event&lt;br /&gt; */&lt;br /&gt;void spis_event_handler(nrf_drv_spis_event_t event)&lt;br /&gt;{&lt;br /&gt; if (event.evt_type == NRF_DRV_SPIS_XFER_DONE)&lt;br /&gt; {&lt;br /&gt; spis_xfer_done = true;&lt;br /&gt; }&lt;br /&gt;}&lt;/p&gt;
&lt;p&gt;int main(void)&lt;br /&gt;{&lt;br /&gt; // Enable the constant latency sub power mode to minimize the time it takes&lt;br /&gt; // for the SPIS peripheral to become active after the CSN line is asserted&lt;br /&gt; // (when the CPU is in sleep mode).&lt;br /&gt; //NRF_POWER-&amp;gt;TASKS_CONSTLAT = 1;&lt;/p&gt;
&lt;p&gt;nrf_drv_spis_config_t spis_config = NRF_DRV_SPIS_DEFAULT_CONFIG;&lt;/p&gt;
&lt;p&gt;spis_config.csn_pin = APP_SPIS_CS_PIN;&lt;br /&gt; spis_config.miso_pin = APP_SPIS_MISO_PIN;&lt;br /&gt; spis_config.mosi_pin = APP_SPIS_MOSI_PIN;&lt;br /&gt; spis_config.sck_pin = APP_SPIS_SCK_PIN;&lt;/p&gt;
&lt;p&gt;spis_config.mode = NRF_SPIS_MODE_0;&lt;br /&gt; spis_config.bit_order = NRF_SPIS_BIT_ORDER_MSB_FIRST;&lt;br /&gt; spis_config.csn_pullup = NRFX_SPIS_DEFAULT_CSN_PULLUP;&lt;br /&gt; spis_config.miso_drive = NRFX_SPIS_DEFAULT_MISO_DRIVE;&lt;br /&gt; spis_config.def = NRFX_SPIS_DEFAULT_DEF;&lt;br /&gt; spis_config.orc = NRFX_SPIS_DEFAULT_ORC;&lt;br /&gt; spis_config.irq_priority = NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY;&lt;/p&gt;
&lt;p&gt;gSpiIfSpiTx.dummy = 0u;&lt;br /&gt; gSpiIfSpiTx.dataLen = 0u;&lt;br /&gt; gSpiIfSpiTx.sequenceCnt = 1u;&lt;br /&gt; gSpiIfSpiTx.syncEnd = SPIIF_HW_SYNC_END;&lt;br /&gt; gSpiIfSpiTx.syncStart = SPIIF_HW_SYNC_START;&lt;br /&gt; gSpiIfSpiTx.dataCrc16 = 0u;&lt;/p&gt;
&lt;p&gt;for (uint8_t i = 0; i&amp;lt;SPI_BLOCK_SIZE; i++)&lt;br /&gt; {&lt;br /&gt; gSpiIfSpiTx.dataBuffer[i] = 0xAA;&lt;br /&gt; }&lt;/p&gt;
&lt;p&gt;nrf_drv_spis_init(&amp;amp;spis, &amp;amp;spis_config, spis_event_handler);&lt;/p&gt;
&lt;p&gt;while (1)&lt;br /&gt; {&lt;br /&gt; memcpy(m_tx_buf, &amp;amp;gSpiIfSpiTx, m_length);&lt;/p&gt;
&lt;p&gt;spis_xfer_done = false;&lt;/p&gt;
&lt;p&gt;nrf_drv_spis_buffers_set(&amp;amp;spis, m_tx_buf, m_length, m_rx_buf, m_length);&lt;/p&gt;
&lt;p&gt;while (!spis_xfer_done)&lt;br /&gt; {&lt;br /&gt; __WFE();&lt;br /&gt; }&lt;br /&gt; }&lt;br /&gt;}&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPI Slave cannot receive data, sending data to master normally</title><link>https://devzone.nordicsemi.com/thread/290006?ContentTypeID=1</link><pubDate>Tue, 19 Jan 2021 12:58:29 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:96e364c3-fc2f-4d0f-9515-cbcdf5b68ea9</guid><dc:creator>J&amp;#248;rgen Holmefjord</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;I&amp;#39;m not sure if I understand what you are asking about. What is&amp;nbsp;tx_size set to? If you set the first and last byte of the&amp;nbsp;m_tx_buf array,I would expect you to get something like &amp;quot;&lt;span&gt;AAFFFFF...00000CC&lt;/span&gt;&amp;quot;, depending on what is in the buffer already.&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;What are you expecting to receive from the STM?&lt;/li&gt;
&lt;li&gt;Have you checked the SPI lines with a logic analyzer, to see if the output is the same that you see in the application?&lt;/li&gt;
&lt;li&gt;Are you using the same SPI Mode configuration on both sides?&lt;/li&gt;
&lt;li&gt;What frequency is the SPI running at?&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;You can also possibly try different GPIOs and/or pull, and drive strength configurations for the pins.&lt;/p&gt;
&lt;p&gt;Best regards,&lt;br /&gt;Jørgen&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>