RE: Watermark interrupt not working correctly with nrf52832 due to spi overhead

pd@learner — Tue, 09 Mar 2021 09:43:36 GMT

I think is what you have (if you read the FIFO status before reading XYZ values out of the FIFO) ie not 2

=> yes if I have read FIFO status before reading XYZ values out of the FIFO then the first time it is 11 i.e watermark interrupt occurs. For next time it is 29.

=>I want to read multiple bytes at a time i.e 12 byte Can you tell me how to read it using nrf spi driver.

RE: Watermark interrupt not working correctly with nrf52832 due to spi overhead

hmolesworth — Tue, 09 Mar 2021 01:17:04 GMT

The watermark register is being set to 10, and so the number of data samples waiting (register bits FSS[4:0]) when reading following the interrupt will be at least 10, which I think is what you have (if you read the FIFO status before reading XYZ values out of the FIFO) ie not 2. It could be more than 10 depending on how long the code takes to eventually read the FIFO status, but following a 10-reading readout it should not go active again until the next 10 samples have been accumulated in the FIFO; FIFO overflow should probably be handled; unexpected results might occur otherwise.

 spi_write_reg(LIS2DH_FIFO_CTRL_REG, 0X8A); 	// FIFO MODE -STREAM ENABLE AND NO SAMPLE 10

Usually the 12-bit XYZ registers - which occupy consecutive bytes on the LIS2DH12 - would be read in a single multi-byte SPI transfer; not quite sure if there is an issue reading just 1 byte at a time.

By the way, using high-drive on /CS, SCK and MOSI allows 8MHz operation.

Note if 10 readings are read out then the FIFO status no longer has those 10 readings to report, and might indeed report 1 or 2 depending how long the code took. Better to read status both before and after reading out the FiFO to see what is happening.