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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Undocumented I2S ratios</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/73569/undocumented-i2s-ratios</link><description>I&amp;#39;m trying to achieve as close as possible to 48KHz (or 24KHz) LRCLK rate, in 24-bit mode (MCK/LRCLK = 48), on an nRF52832. With the values defined in `nrf_i2s_mck_t ` the closest I can get is 32DIV15 (44.4 KHz, -7%) or 32DIV30 (22.2 KHz, -7%). However</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Thu, 08 Apr 2021 13:56:35 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/73569/undocumented-i2s-ratios" /><item><title>RE: Undocumented I2S ratios</title><link>https://devzone.nordicsemi.com/thread/303811?ContentTypeID=1</link><pubDate>Thu, 08 Apr 2021 13:56:35 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:34df4836-f6fd-4ef2-8d0b-8d4c2ac1e1c6</guid><dc:creator>H&amp;#229;kon Alseth</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;This formula will give you a ballpark number, if you change the divider to be 32M instead of 16M:&lt;/p&gt;
&lt;p&gt;&lt;a href="https://devzone.nordicsemi.com/f/nordic-q-a/391/uart-baudrate-register-values/2046#2046"&gt;https://devzone.nordicsemi.com/f/nordic-q-a/391/uart-baudrate-register-values/2046#2046&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;However, since this&amp;nbsp;specific module uses&amp;nbsp;a pure clk division, and not a baudrate generator, it will not be accurate for all frequencies that you input. for instance, the formula does not match specifically for the frequency that you request.&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Kind regards,&lt;/p&gt;
&lt;p&gt;Håkon&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Undocumented I2S ratios</title><link>https://devzone.nordicsemi.com/thread/303226?ContentTypeID=1</link><pubDate>Tue, 06 Apr 2021 14:30:21 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:ad631dcc-e182-47f9-aa52-b00c8def3a31</guid><dc:creator>Charlie</dc:creator><description>&lt;p&gt;Thanks for the information, this all makes sense. There&amp;#39;s just one bit I&amp;#39;m unclear about&lt;/p&gt;
[quote userid="2115" url="~/f/nordic-q-a/73569/undocumented-i2s-ratios/303186#303186"] If we&amp;nbsp;write 0x12000000 to this register, we should get ~2.2857 MHz[/quote]
&lt;p&gt;How do you get from the register value (0x12000000) to the corresponding division ratio (14)? I initially thought that the register value was just the division ratio with the bits reversed, but this doesn&amp;#39;t seem to be the case?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Undocumented I2S ratios</title><link>https://devzone.nordicsemi.com/thread/303186?ContentTypeID=1</link><pubDate>Tue, 06 Apr 2021 13:29:52 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:88cc3861-a6f4-4c0c-a421-b1a81ca07bc3</guid><dc:creator>H&amp;#229;kon Alseth</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;The base frequency is 32 MHz, so your wanted mclk must be a integer division of this base clock.&lt;/p&gt;
&lt;p&gt;2 ch * 24 bit * 48 kHz = 2.304 MHz.&lt;/p&gt;
&lt;p&gt;32M / 2.304M = 13.89 (similar scenario if we look at 24 kHz sampling rate)&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Rounding to the closest integer of 14.&lt;/p&gt;
&lt;p&gt;32M/14 = 2.2857 MHz&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;As you have already found out:&lt;/p&gt;
&lt;p&gt;Wrt. the register value of div14, you can look at the definition:&lt;/p&gt;
&lt;p&gt;&lt;a href="https://infocenter.nordicsemi.com/topic/ps_nrf52840/i2s.html?cp=4_0_0_5_10_9_13#register.CONFIG.MCKFREQ"&gt;https://infocenter.nordicsemi.com/topic/ps_nrf52840/i2s.html?cp=4_0_0_5_10_9_13#register.CONFIG.MCKFREQ&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;div15 = 0x11000000&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;so If we&amp;nbsp;write 0x12000000 to this register, we should get ~2.2857 MHz, which seems to be the case when I look at it with a logic analyzer:&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;img src="https://devzone.nordicsemi.com/resized-image/__size/640x480/__key/communityserver-discussions-components-files/4/pastedimage1617715371630v1.png" alt=" " /&gt;&lt;/span&gt;&amp;nbsp;&lt;/p&gt;
[quote user=""]Is there any reason to prefer the values in `nrf_i2s_mck_t` over the experimentally-determined rates? The custom values seem to work with my amplifier in practice, I can&amp;#39;t hear any obvious issues.[/quote]
&lt;p&gt;The list was shortened to the most match the most popular settings, so it should not be an issue to use the register value that you found now.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
[quote user=""]Additionally, are there any better values than the ones I found experimentally? I couldn&amp;#39;t find any documentation about how the register value corresponds to a clock frequency, so I was just guessing&amp;nbsp;based on `I2S_CONFIG_MCKFREQ_MCKFREQ` definitions in `nrf52_bitfields.h`.[/quote]
&lt;p&gt;No, unfortunately. The value must be an integer division of the base clock.&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Kind regards,&lt;/p&gt;
&lt;p&gt;Håkon&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>