https://devzone.nordicsemi.com/f/nordic-q-a/73624/nrf5340-how-does-the-adc-gain-block-work-and-what-does-the-eg1-6-to-eg1-7-29-12-1-saadc-electrical-specification-meanHow does the ADC gain block work. Suppose using Vdd=3.3V as ADC reference, analog signal input from 0 to 3V and gain 1/4 What will be the ADC core voltage for single ended ADC measurement is it 0 to VDD/4 ( 0 to 0.825V) or double 0 to Vdd/2 (en-USTelligent Community 13Wed, 07 Apr 2021 09:41:45 GMThttps://devzone.nordicsemi.com/thread/303419?ContentTypeID=1Wed, 07 Apr 2021 09:41:45 GMT137ad170-7792-4731-bb38-c0d22fbe4515:4bb424f3-7bc2-4b28-9745-200f94a8145chaakonsh<p>The gain error is independent of any offset calibration. Gain calibration is done during manufacturing, so the error from the gain stage is characterized after gain calibration.&nbsp;</p><div style="clear:both;"></div>https://devzone.nordicsemi.com/thread/303322?ContentTypeID=1Wed, 07 Apr 2021 02:00:21 GMT137ad170-7792-4731-bb38-c0d22fbe4515:6b3969fa-5b18-4d14-89fa-42709a8eaabbSyedSajid<p>Thanks Haakonsh, on your point 3&nbsp;the error specification mentioned&nbsp; is it before performing any calibration on the gain/offset or after&nbsp;</p> <div class="ms-editor-squiggler" style="background:initial;border:initial;border-collapse:initial;border-radius:initial;border-spacing:initial;box-shadow:initial;color:initial;clear:initial;cursor:initial;display:block;float:initial;font:initial;height:0px;letter-spacing:initial;list-style:initial;margin:initial;overflow:initial;padding:initial;table-layout:initial;text-align:initial;text-decoration:initial;text-indent:initial;text-overflow:initial;text-shadow:initial;text-transform:initial;vertical-align:initial;white-space:initial;width:initial;"></div><div style="clear:both;"></div>https://devzone.nordicsemi.com/thread/303119?ContentTypeID=1Tue, 06 Apr 2021 11:59:22 GMT137ad170-7792-4731-bb38-c0d22fbe4515:32b70fb2-be4f-4e12-90b5-81af72579cd2haakonsh<ol> <li>The input range is 0-VDD with a reference at VDD/4. This means that you will need to set the appropriate gain, f.ex. 1/4, in order to scale the input voltage range to the reference voltage range.&nbsp;<br /><br /></li> <li>See (1).<br /><br /></li> <li>The error in the gain stage has not yet been characterized on the nRF5340, but I would be surprised if it was not very similar to the nRF52&#39;s&nbsp;<a title="SAADC electrical specification" href="https://infocenter.nordicsemi.com/topic/ps_nrf52840/saadc.html?cp=4_0_0_5_22_9_0#unique_1557537733">SAADC electrical specification</a>.<br />It is error/noise introduced in the gain stage, without&nbsp;any input offset.&nbsp;&nbsp;</li> </ol><div style="clear:both;"></div>