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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>SPIM/UARTE register conflict with hal_nordic</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/73678/spim-uarte-register-conflict-with-hal_nordic</link><description>We are using the Nordic fork of Zephyr on nRF5340. 
 Looking at the serial interface peripherals (SPI/I2C/UART), we understand that these have shared resources and only one peripheral with a given ID can be active. 
 However there is a conflict with the</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Thu, 08 Apr 2021 16:50:07 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/73678/spim-uarte-register-conflict-with-hal_nordic" /><item><title>RE: SPIM/UARTE register conflict with hal_nordic</title><link>https://devzone.nordicsemi.com/thread/303859?ContentTypeID=1</link><pubDate>Thu, 08 Apr 2021 16:50:07 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:1ae17db5-db34-4485-b74d-e0e78ab42ab2</guid><dc:creator>J&amp;#248;rgen Holmefjord</dc:creator><description>&lt;p&gt;Yes, you should make sure to set&amp;nbsp;&lt;span&gt;p_config-&amp;gt;&lt;/span&gt;&lt;span&gt;dcx_pin&lt;/span&gt;&lt;span&gt;&amp;nbsp;== NRFX_SPIM_PIN_NOT_USED for all other instances than SPIM4, then the init function should not change this and make issues for the UARTE instances using this register.&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;The uninit-function seems to contain a bug, and is something we should handle better. Previous chips have not had these issues, as nRF52 series ICs had separate base addresses for UART(E) instances (not shared with SPI/TWI), and nRF91 did not include the 32MHz high-speed SPI instance, so there was no DCX support at all. I will report this issue to our developers to get it fixed in future releases of NRFX.&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPIM/UARTE register conflict with hal_nordic</title><link>https://devzone.nordicsemi.com/thread/303387?ContentTypeID=1</link><pubDate>Wed, 07 Apr 2021 08:24:59 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:adf01f52-49b1-4d8c-a1e0-62dcecef6d19</guid><dc:creator>Stephan Walter</dc:creator><description>&lt;p&gt;Hi J&amp;oslash;rgen,&lt;/p&gt;
&lt;p&gt;thanks for the quick response.&lt;/p&gt;
&lt;p&gt;So leaving PSELDCX at 0 for SPIM0 to SPIM3 is ok, I assume?&lt;/p&gt;
&lt;p&gt;In any case there is still a problem in the function &lt;span class="pl-en"&gt;nrfx_spim_uninit&lt;/span&gt;:&lt;/p&gt;
&lt;p&gt;&lt;a href="https://github.com/zephyrproject-rtos/hal_nordic/blob/fc301b97581d01cb5be47f837087a41632070434/nrfx/drivers/src/nrfx_spim.c#L472"&gt;https://github.com/zephyrproject-rtos/hal_nordic/blob/fc301b97581d01cb5be47f837087a41632070434/nrfx/drivers/src/nrfx_spim.c#L472&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;It will call &lt;span class="pl-c1"&gt;nrf_gpio_cfg_default&lt;/span&gt;(0).&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPIM/UARTE register conflict with hal_nordic</title><link>https://devzone.nordicsemi.com/thread/303383?ContentTypeID=1</link><pubDate>Wed, 07 Apr 2021 08:12:08 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:9c7243f4-af57-4f09-bb75-76c52ba75d34</guid><dc:creator>J&amp;#248;rgen Holmefjord</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;DCX functionality is only supported in SPIM4 (32 MHz High-speed instance), see &amp;quot;Configuration&amp;quot; column next to each instance in&amp;nbsp;&lt;a title="Registers" href="https://infocenter.nordicsemi.com/topic/ps_nrf5340/spim.html?cp=3_0_0_6_29_6#topic"&gt;Registers&lt;/a&gt;. SPIM4 does not share any resources with UARTE, as there is no UARTE4 instance, see&amp;nbsp;&lt;a title="Peripheral instantiation" href="https://infocenter.nordicsemi.com/topic/ps_nrf5340/chapters/memory/appmem.html?cp=3_0_0_4_2_0#instantiation"&gt;Peripheral instantiation&lt;/a&gt;.&lt;/p&gt;
&lt;p&gt;You should not enable DCX for other instances of SPIM when initializing the SPIM driver.&lt;/p&gt;
&lt;p&gt;Best regards,&lt;br /&gt;Jørgen&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>