RE: nRF52840-QIAA Shematic evaluation

Marjeris Romero — Thu, 15 Apr 2021 12:20:01 GMT

Happy to help!

RE: nRF52840-QIAA Shematic evaluation

Alberto Garcia Giro — Wed, 14 Apr 2021 21:00:14 GMT

Hello Marjeris,

Sincerely thankou very much for your great and clear answere!

RE: nRF52840-QIAA Shematic evaluation

Marjeris Romero — Wed, 14 Apr 2021 20:42:43 GMT

Hi Alberto,

[quote user=""]Point 1
For the power supply I am using a schematic as shown in figure 16 (page 63) of the datasheet and also used in the nRF52840 Development Kit. Hi Voltage Mode, DC/DC for REG0 and REG1 enabled.
In this scheme the power input is 3.3V on VDDH (only this pin Y2), while all the VDD pins are power output from the nRF52840. I am not using VDD to power any other circuitry external to the nRF52840.
1-) Is this correct? Just have the VDDH pin (Y2) as power input. [/quote]

Yes, in High voltage mode, as we call this configuration, the supply voltage is only connected to the VDDH pin and the VDD pin is not connected to any voltage supply. See https://infocenter.nordicsemi.com/topic/ps_nrf52840/power.html?cp=4_0_0_4_2_0#topic

[quote user=""]2-) According I understood with this power supply topology the DIO voltage levels can be configured. Am I right? [/quote]

Yes, in High Voltage mode the GPIO high level equals the level specified in register REGOUT0.

[quote user=""]3-) I need to use two independent UART interfaces, can I set the voltage level on one interface to 1.8V and on the other interface to 3.3V? Or both UART interfaces must work at the same voltage level (3.3V preferably)?[/quote]

Not possible, REGOUT0 will set the high voltage level for all GPIO.

[quote user=""]Point 2
In my application I need to use two independent UART communications, as I read in the datasheet the UART signals can be routed to any DIO pin.I named each interface UARTA and UARTB. So I have connected
UARTB_TX -> P0.30 (B9)
UARTB_RX -> P0.28 (B11)
UARTA_TX -> P0.29 (A10)
UARTA_RX -> P0.02 (A12)
UARTA__CTS -> P1.15 (A14)
UARTA_RTS -> P1.13(A16)

1-) Are the connections correct?[/quote]

Looks good.

[quote user=""]2-) Can I use two independent UART interfaces without shared resources conflict?[/quote]

Yes. UARTE0 and UARTE1 have different peripheral IDs so they do not share resources, see the instantiation table: https://infocenter.nordicsemi.com/topic/ps_nrf52840/memory.html?cp=4_0_0_3_1_3#topic

[quote user=""]Point 3
1-) If the USB interface is not used, can the USB pins be left open?[/quote]

Yes, you can let the DECUSB, D+ and D- floating and I recommend grounding VUSB as shown in the reference design:

[quote user=""]

Point 4-)

On pin 1 of the programming connectors (debug in and trace P18, P25), what should I connect VDDH or VDDD?

[/quote]

From Segger website: https://www.segger.com/products/debug-probes/j-link/technology/interface-description/
Pin 1 is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators and to control the output logic levels to the target. It should match the GPIO high voltage level.

Best regards,

Marjeris