RE: Double buffered SPIM TXD and RXD registers on nrf5340

Alexander Thorstensen — Thu, 15 Apr 2021 11:36:13 GMT

I expanded the "broken example" from my original post to use two independent rx_buffers, rx_buff[0], rx_buff[1]

As before all rx_buff memory is painted with 0xAA before SPIM transaction, and the buffers are logged before and after the transactions has completed. This gave the result captured below:

Based on this result it seems like the double buffered registers are reloaded at the next TASK_START trigger, even though list mode is used.

My hope was that the SPIM would hold off reloading until a TASK_STOP trigger has been received. I am using SPIM with a counter to implement a burst read from a chip that requires slave select to deactivate between every register access, and I was hoping to use double buffered RXD / TXD to prime for burst n+1 at the start for burst n.

The obvious solution would be to start transactions from a drdy triggered ISR, or to prime the SPIM for the next burst at the end of every burst, but this will result in quite tight ISR latency requirements.

Suggestions to alternative solutions are most welcome :)