https://devzone.nordicsemi.com/f/nordic-q-a/7465/spi-communication-rising-edge-of-clockHello, How can I have the rising edge of my clock to be less than 40nm? I am currently using a 4GHZ clock cycle for my SPI communication? Thank you.en-USTelligent Community 13Sat, 06 Jun 2015 02:56:15 GMThttps://devzone.nordicsemi.com/thread/26584?ContentTypeID=1Sat, 06 Jun 2015 02:56:15 GMT137ad170-7792-4731-bb38-c0d22fbe4515:0655c77d-fe0a-43bf-9a7b-cbbe263883deRK<p>Your question really doesn&#39;t make any sense at all.</p> <p>40nm? 40 nanometers? Did you mean 40ns? Even if you did, 40ns is the total cycle time for 25MHz which is somewhat less than 4GHz, a frequency 500 times beyond what the nrf51 series supports for SPI. In fact the actual product sheet for the 51822 says 4MHz is the max.</p> <p>That product sheet also gives the clock rise/fall time as 100ns, so you can&#39;t have 40ns, even if that&#39;s what you meant.</p><div style="clear:both;"></div>https://devzone.nordicsemi.com/thread/26583?ContentTypeID=1Fri, 05 Jun 2015 21:25:55 GMT137ad170-7792-4731-bb38-c0d22fbe4515:0c875e6f-2fe6-405c-8773-0333435d719fWojtek<p>I don&#39;t know what is the time of edge rising, but according to reference manual SPI Master on nrf51822 allows max data rate of 8Mbps</p><div style="clear:both;"></div>