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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>High drive &amp;amp; QSPI pin on nRF52840</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/76277/high-drive-qspi-pin-on-nrf52840</link><description>Hello, 
 In a design we plan to have 2 x SPI, 1 x QSPI and 1 x I2C interface. For the SPI we plan to use one @32MHz and the other @8MHz. 
 Please confirm there no &amp;quot;instance issue&amp;quot; with all these interfaces ? 
 Could you also please confirm that High drive</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Mon, 14 Jun 2021 14:58:15 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/76277/high-drive-qspi-pin-on-nrf52840" /><item><title>RE: High drive &amp; QSPI pin on nRF52840</title><link>https://devzone.nordicsemi.com/thread/315192?ContentTypeID=1</link><pubDate>Mon, 14 Jun 2021 14:58:15 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:8e55d689-5a6e-468f-8e23-a5dd984eb568</guid><dc:creator>NicolasVoirol</dc:creator><description>&lt;p&gt;Great ... Thx&lt;br /&gt;Have a nice evening !&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: High drive &amp; QSPI pin on nRF52840</title><link>https://devzone.nordicsemi.com/thread/315188?ContentTypeID=1</link><pubDate>Mon, 14 Jun 2021 14:56:03 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:3e4f64c0-bdcc-4dcc-94dc-0ac8793bfb07</guid><dc:creator>Einar Thorsrud</dc:creator><description>&lt;p&gt;&lt;span&gt;Hi&amp;nbsp;Nicolas,&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;Yes, that is correct. Pins not marked as &amp;quot;Standard drive, low frequency I/O only&amp;quot; can be used with high frequency and/or high drive.&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: High drive &amp; QSPI pin on nRF52840</title><link>https://devzone.nordicsemi.com/thread/315187?ContentTypeID=1</link><pubDate>Mon, 14 Jun 2021 14:53:16 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:fa217661-d3c1-49b5-935f-2c9af1918c22</guid><dc:creator>NicolasVoirol</dc:creator><description>&lt;p&gt;Hi Einar,&lt;br /&gt;Ok thanks for confirming this.&lt;/p&gt;
&lt;p&gt;Could you also please confirm that High drive pins (-&amp;gt; for 32Mbits SPI) are those where nothing is written in the &amp;quot;recommended usage&amp;quot; column.&lt;/p&gt;
&lt;p&gt;&lt;a href="https://infocenter.nordicsemi.com/topic/ps_nrf52840/pin.html?cp=4_0_0_6_0"&gt;infocenter.nordicsemi.com/.../pin.html&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;For some pins it is written &amp;quot;Standard drive, low frequency I/O only&amp;quot; so I assume that others GPIO can be configured as High drive.&lt;br /&gt;For QSPI we plan to use the recomended ones (P0.18, P0.19, P0.21 - P0.24)&lt;/p&gt;
&lt;p&gt;Thx&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: High drive &amp; QSPI pin on nRF52840</title><link>https://devzone.nordicsemi.com/thread/315180?ContentTypeID=1</link><pubDate>Mon, 14 Jun 2021 14:34:57 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:d67b4fd5-de77-4589-b076-43ddb0b03db0</guid><dc:creator>Einar Thorsrud</dc:creator><description>&lt;p&gt;Hi&amp;nbsp;Nicolas,&lt;/p&gt;
&lt;p&gt;That is no problem. You can see that from the &lt;a href="https://infocenter.nordicsemi.com/topic/ps_nrf52840/memory.html?cp=4_0_0_3_1_3#topic"&gt;instantiation table&lt;/a&gt;&amp;nbsp;(peripherals with the same ID use the same HW resources and cannot be used together).&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>