https://devzone.nordicsemi.com/f/nordic-q-a/76695/spi-slave-questionHi: I have write a spi slave, and write a spi master on STM32, It can receive data from STM32,But I have no time to prepare the response data. as the code below, I can receive the command 0x01 from master, But the response data can only be responseen-USTelligent Community 13Mon, 12 Jul 2021 08:20:23 GMThttps://devzone.nordicsemi.com/thread/319531?ContentTypeID=1Mon, 12 Jul 2021 08:20:23 GMT137ad170-7792-4731-bb38-c0d22fbe4515:ca0fd887-c51f-4866-8c63-64aa810495efJared<p>Then you have to wait for the next transaction. The data that is intended to be sent in a transaction has to be ready to be clocked out&nbsp;before the transaction starts.&nbsp;</p><div style="clear:both;"></div>https://devzone.nordicsemi.com/thread/317379?ContentTypeID=1Mon, 28 Jun 2021 06:45:22 GMT137ad170-7792-4731-bb38-c0d22fbe4515:a8e7aca9-6949-41a2-a53a-9b27af8f3552great-master<p>I coun&#39;t set my tx buffer exactly, because I don&#39;t know which command will be receive,I need to know waht the master request .My english is not very good, can you understand?</p><div style="clear:both;"></div>https://devzone.nordicsemi.com/thread/317155?ContentTypeID=1Fri, 25 Jun 2021 08:37:39 GMT137ad170-7792-4731-bb38-c0d22fbe4515:b2aa92a7-2870-490c-a179-bde96aea2761Jared<p>Hi,</p> <p></p> <p>&nbsp;</p> [quote user=""]But the response data can only be response in next reqest, At the first request, m_rx_buf buffer have no data.[/quote] <p>This is as I would expect based on the SPI protocol. The SPI protocol works as shifting register on both sides, thus you should clock out data as you receive data. You set the tx buffer first after you have received data and the transaction has been completed. How would you then expect it to be able to send the data in that very same transaction?</p> <p>Maybe I misunderstood you, in that case please elaborate on your question.</p> <p>best regards</p> <p>Jared&nbsp;</p><div style="clear:both;"></div>