Question on QSPI registers CINSTRCONF and CINSTRDAT0

RE: Question on QSPI registers CINSTRCONF and CINSTRDAT0

sshenoy105 — Fri, 13 Aug 2021 18:50:08 GMT

ok.. thanks for confirming and it is greatly appreciated.. Looks like using your QSPI interface with many display controllers is going to be challenging.

if i have any further questions, i will file another ticket..

RE: Question on QSPI registers CINSTRCONF and CINSTRDAT0

Simonr — Fri, 13 Aug 2021 11:47:58 GMT

Sorry, my bad. I got caught up in the QSPI part. I'm afraid that custom instructions will work as a standard SPI where you have one signal for TX and another one for RX. SIO0 (out) and SIO1 (in) in this instance.

Best regards,

Simon

RE: Question on QSPI registers CINSTRCONF and CINSTRDAT0

sshenoy105 — Thu, 12 Aug 2021 18:27:49 GMT

ok.. I looked at the latest datasheet and it is not much different as far as the context is concerned (please correct me if i missed anything there).. the question remains though since you did not answer what I had highlighted..

Are you expecting the custom instruction to be written over all 4 IOs?
No.. It is clear to me how custom instruction works from POV of sending it from MCU

what I want to know is if the response data )from QSPI slave) in CINSTRDAT0 and CINSTRDAT1 contain ONLY bits that come in via SIO1 as shown in Figure 4 . As in MCU sends command/data in SIO0 and does MCU expect the response from QSPI slave ONLY in SIO1 ? The reason I ask is many display controllers, sense what's coming in via SIO0 and send response on the same SIO0 line.. can you please confirm ?

RE: Question on QSPI registers CINSTRCONF and CINSTRDAT0

Simonr — Thu, 12 Aug 2021 13:25:25 GMT

First off, is there a reason you're using the nRF5340 OPS (v0.5) instead of the official product specification? The OPS was intended for the engineering ICs, and can not be counted as complete.

I assume this is the figure you're referring to (it's no longer Figure 116 in the latest PS revision).

Are you expecting the custom instruction to be written over all 4 IOs? As stated in section 7.25.7 Sending custom instructions: "The custom instruction is sent when the CINSTRCONF register is written and it is always sent on a single data line SPI interface." Which is why all custom instruction data goes over IO0 and IO1.

Best regards,

Simon

RE: Question on QSPI registers CINSTRCONF and CINSTRDAT0

sshenoy105 — Wed, 11 Aug 2021 20:12:07 GMT

the title should have been

Question on QSPI registers