QSPI read/write to flash with page cache (MX35LF4GE4AD)

RE: QSPI read/write to flash with page cache (MX35LF4GE4AD)

Simonr — Thu, 07 Oct 2021 13:27:39 GMT

Hi Elliot

I'm afraid we don't have a way to enable 16 bit addressing mode. Our QSPI peripheral is best suited for NOR flash devices and XIP. I guess you can use only custom instructions, but that will only go over one data line and regular SPI would then give you much better performance.

Best regards,

Simon

RE: QSPI read/write to flash with page cache (MX35LF4GE4AD)

emakuh — Wed, 06 Oct 2021 23:14:36 GMT

It looks like the page caching mechanism is a common approach after reviewing some data sheets for other larger capacity (4 Gb+) flash chips.

All of these chips support a 24 bit read but not a 24 bit write (for the page cache). Is there any way to enable a 16 bit addressing mode in the Nordic QSPI interface?

datasheet.datasheetarchive.com/.../DSAIH000222082.pdf

www.mouser.com/.../AllianceMemory_SPI_NAND_Flash_July2020_Rev1_0-1893515.pdf

RE: QSPI read/write to flash with page cache (MX35LF4GE4AD)

emakuh — Wed, 06 Oct 2021 22:25:57 GMT

Note: I have a duplicate post that I accidentally marked as solved even though it wasn't. I created this so people can provide feedback.

devzone.nordicsemi.com/.../qspi-read-write-to-flash-with-page-cache-mx35lf4ge4ad