https://devzone.nordicsemi.com/f/nordic-q-a/8045/nrf51-patch-unit-pu-and-ahb-multi-layer-interface-amliHeader for nRF51 (nrf51.h) mentions two peripheral blocks completely missing from chip documentation. Are they functioning? If so, the comment for PATCHADDR field of PU says it&#39;s relative. Is it relative to the address of patched instruction (flash worden-USTelligent Community 13Thu, 09 Jul 2015 07:28:02 GMThttps://devzone.nordicsemi.com/thread/28844?ContentTypeID=1Thu, 09 Jul 2015 07:28:02 GMT137ad170-7792-4731-bb38-c0d22fbe4515:793355c7-b8d0-4199-a506-5daa36f97568Chinook<p>DFU is somewhat different and FPB on higher Cortex-M&#39;s is known. But anyway thanks.</p><div style="clear:both;"></div>https://devzone.nordicsemi.com/thread/28843?ContentTypeID=1Thu, 09 Jul 2015 07:18:48 GMT137ad170-7792-4731-bb38-c0d22fbe4515:04618f95-fb1b-4a8a-8722-e97757880dcdSusheel Nuguru<p>Hi Chinook, PU is not supported anymore. I have created a ticket to remove those from the header files. We have DFU now for firmware updates on nRF51 and on nRF52 we have FPB module on ARM Cortex-M4. More details on FPB can be found <a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0439b/BABJEBBC.html">here</a></p> <p>Regarding RAM priority in AMLI, it is same as interrupt priority. Lower number means higher priority, i.e. 0 is highest priority.</p><div style="clear:both;"></div>