SPI Slave event handler not triggered when CS arrested

RE: SPI Slave event handler not triggered when CS arrested

Sivashankar — Fri, 15 Oct 2021 10:18:56 GMT

Ref: infocenter.nordicsemi.com/.../nRF52_PAN_109_add_v1.1.pdf

3.9 SPIS workaround: Trigger GPIOTE on the CSN signal Use a GPIOTE event to wake the CPU when there is a falling edge on the SPIS CSN signal. 1. Set up a GPIOTE channel to generate events on falling edges of the CSN signal. 2. Enable interrupt generation for this event in the INTENSET register, and enable this interrupt in NVIC. 3. Handle the NVIC interrupt by clearing the generated event in the GPIOTE EVENT register and NVIC before putting CPU to sleep again. Pros: Specific workaround for SPIS without very large increase of current consumption. Cons: Workaround requires a GPIOTE, some increase of current consumption

Will this work?

RE: SPI Slave event handler not triggered when CS arrested

Sivashankar — Mon, 11 Oct 2021 11:46:37 GMT

Hi Turbo,

I've SPIS init sequence as so, I've followed SPIS SDK example, though it's not very clear about Easy DMA etc.,

nrf_drv_spis_config_t spis_config = NRF_DRV_SPIS_DEFAULT_CONFIG;
spis_config.csn_pin               = APP_SPIS_CS_PIN;
spis_config.miso_pin              = APP_SPIS_MISO_PIN;
spis_config.mosi_pin              = APP_SPIS_MOSI_PIN;
spis_config.sck_pin               = APP_SPIS_SCK_PIN;

APP_ERROR_CHECK(nrf_drv_spis_init(&spis, &spis_config, spis_event_handler));

Could you please share me any reference for the same.

Thanks,

RE: SPI Slave event handler not triggered when CS arrested

Turbo J — Mon, 11 Oct 2021 11:38:22 GMT

Read the SPIS chapter in the PS.

For the SPIS to work, you set up RX and TX (Easy-)DMA buffers before the transaction starts. Once the transactions starts with the CS being pulled low, the CPU looses access to those buffers.

Once the transaction finishes with CS=High, the interrupt handler will fire via END event.