nRF52833 Power Scheme

RE: nRF52833 Power Scheme

Martin Sivertsen — Mon, 25 Oct 2021 12:37:06 GMT

Hello Harry,

We do not usually share DCDC efficiency plots since they can be more confusing than clarifying since the power and clock system automatically turns on and off resources based on peripherals and power modes.

What we usually do is to give 1:1 comparison between LDO and DCDC mode for different use cases (e.g. TX 8 dBm, TX 0 dBm, CPU running Coremark, RX BLE1M).

For example: At TX 8 dBm (only Radio) we get ~26 mA with DCDC and ~30 mA with LDO at 1.7 volt. At 3.0 volt the numbers are ~14 mA and 30 mA so the statement is correct, higher difference between input voltage and output voltage will give better efficiency advantage for DCDC.

I hope this is somewhat clarifying, we can get more data (comparison values) for you if you need.

Best regards,

Martin S.

RE: nRF52833 Power Scheme

harrykuang — Fri, 22 Oct 2021 17:50:36 GMT

Hi Martin,

Yes VDD = 1.8V since that is our IO system IO voltage level. REG0 is in normal voltage mode. In terms of HW VDD and VDDH are connected on the nRF.

Harry

RE: nRF52833 Power Scheme

Martin Sivertsen — Fri, 22 Oct 2021 10:01:27 GMT

Hi Harry,

Am I correct in assuming you have VDD = 1.8?

Have you configured the nRF52833 to use high voltage mode (REG0) or normal voltage mode?

Best regards,

Martin S.

RE: nRF52833 Power Scheme

Martin Sivertsen — Fri, 22 Oct 2021 09:45:56 GMT

Hi Harry,

I have forwarded your inquiry to the IC development team and will update you as soon as I get a reply.

Best regards,

Martin S.