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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Zephyr QSPI Enter 32-bit Address Mode</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/81114/zephyr-qspi-enter-32-bit-address-mode</link><description>I&amp;#39;ve made a basic QSPI setup for an MT25QU512. By default the QSPI driver is using 24-bit addressing. To access all of the memory, I&amp;#39;d like to set up the QSPI driver to use 32-bit addressing (via address-size-32). In order to do that, a command needs</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Wed, 27 Oct 2021 12:13:51 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/81114/zephyr-qspi-enter-32-bit-address-mode" /><item><title>RE: Zephyr QSPI Enter 32-bit Address Mode</title><link>https://devzone.nordicsemi.com/thread/336194?ContentTypeID=1</link><pubDate>Wed, 27 Oct 2021 12:13:51 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:0cf620e0-c78a-4e1d-9cda-a85e346d4f10</guid><dc:creator>Simonr</dc:creator><description>&lt;p&gt;Hi&lt;/p&gt;
&lt;p&gt;The nrfx_qspi library uses the NRF_QSPI_ADDRMODE_ to set the address mode to 24 bit by default, but in nrf_qspi.h there is also a NRF_QSPI_ADDRMODE_32BIT that can be used to set 32-bit addressing I think. Alternatively you can send this op code to the QSPI flash using a custom instruction which our QSPI peripheral supports. Here is an example snippet of how you can send an OP code to the flash device. the .opcode needs to be 0xB7 in your specific case. Please note that you&amp;#39;ll need to declare this function somewhere.&lt;/p&gt;
&lt;p&gt;&lt;pre class="ui-code" data-mode="text"&gt;nrfx_err_t CINSTR_function(size_t OPCODE)
{
	
	nrf_qspi_cinstr_conf_t cinstr_cfg = {
		.opcode 	= OPCODE,
		.length 	= NRF_QSPI_CINSTR_LEN_1B,
		.io2_level	= false,
		.io3_level 	= false,
		.wipwait 	= true,
		.wren 		= true
	};

    int err = nrfx_qspi_cinstr_xfer(&amp;amp;cinstr_cfg, NULL, NULL);
    if (err != NRFX_SUCCESS) {
	    }


return NRFX_SUCCESS;
}
&lt;/pre&gt;&lt;/p&gt;
&lt;p&gt;Best regards,&lt;/p&gt;
&lt;p&gt;Simon&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>