case about GPIO equivalent circuit diagram when no power supply

RE: case about GPIO equivalent circuit diagram when no power supply

Vidar Berg — Thu, 09 Dec 2021 09:14:22 GMT

Hi Peter.Min,

I'm not familiar with the internal design of the pad, but it seems like the circuit you drew with the diodes is typically how ESD protection is implemented in IC designs. But like I said, It's not safe to apply voltage on the pad when VDD is 0V.

Kind regards,

Vidar

RE: case about GPIO equivalent circuit diagram when no power supply

peter.min — Thu, 09 Dec 2021 01:17:35 GMT

Hi Vidar Berg,

In actual measurement, power supply behavior through IO port did occur, and there is about 0.6V voltage drop.

Is it equivalent to the following circuit?

Thank you very much.
Kind regards,
Peter.Min

RE: case about GPIO equivalent circuit diagram when no power supply

Vidar Berg — Wed, 08 Dec 2021 12:38:22 GMT

Hi,

You exceed the Absolute maximum ratings for the IC if you apply more than VDD+0.3 V on the IO pin, and this may cause permanent damage to the chip.

When you apply 3.3 volts on the GPIO pin while VDD=0V you will basically end up back powering the chip via the pin, hence the voltage drop.

Best regards,

Vidar