Error in SVC handler in NRF52 SDK 0.9.1 with S132

RE: Error in SVC handler in NRF52 SDK 0.9.1 with S132

Susheel Nuguru — Tue, 09 Feb 2016 07:03:04 GMT

Hi Alex, it is bit 2 (not bit 3) that we need to test.

RE: Error in SVC handler in NRF52 SDK 0.9.1 with S132

Susheel Nuguru — Thu, 23 Jul 2015 17:15:48 GMT

I have been looking into this for some time now, I really think that checking bit 2 in LR would be best on Cortex-M4. I will have discussion with softdevice team to correct this. This is a confirmed bug, we have not noticed it on softdevice because in our examples, we have no exception entry with FPU registers pushed onto stack.

RE: Error in SVC handler in NRF52 SDK 0.9.1 with S132

Susheel Nuguru — Wed, 22 Jul 2015 08:03:01 GMT

Thanks for updating us, I will notify this to the softdevice team immediately. I appreciate you coming here with this good information.

RE: Error in SVC handler in NRF52 SDK 0.9.1 with S132

Alex Young — Wed, 22 Jul 2015 08:00:30 GMT

Hi Aryan,

Thanks for looking into this. I have found that the same error exists later in the handler as well at 0x0001d62c.

Patching the instruction sequence at both locations to:

tst lr, #4
ite eq
mrseq r1, MSP
mrsne r1, PSP
nop
nop

gives a working system.

RE: Error in SVC handler in NRF52 SDK 0.9.1 with S132

Susheel Nuguru — Tue, 21 Jul 2015 11:57:53 GMT

Hi Alex, I will start to look into it tomorrow.