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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>nRF53 DPPI and low-power/low-latency</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/83630/nrf53-dppi-and-low-power-low-latency</link><description>I am using the DPPI feature in the nRF5340 to trigger an SPI transaction from a GPIO edge with a delay. 
 In more detail: 
 GPIOTE IN event triggers RTC clear task 
 RTC compare event triggers SPIM start task 
 This works fine so far, now I am looking</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Tue, 18 Jan 2022 08:14:31 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/83630/nrf53-dppi-and-low-power-low-latency" /><item><title>RE: nRF53 DPPI and low-power/low-latency</title><link>https://devzone.nordicsemi.com/thread/348190?ContentTypeID=1</link><pubDate>Tue, 18 Jan 2022 08:14:31 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:621ce0a1-2ca9-43af-97f3-fda4c0552e26</guid><dc:creator>Kazi Afroza Sultana</dc:creator><description>&lt;p&gt;Thank you Stephan. I am glad to hear that.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;BR&lt;/p&gt;
&lt;p&gt;Kazi Afroza Sultana&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF53 DPPI and low-power/low-latency</title><link>https://devzone.nordicsemi.com/thread/347916?ContentTypeID=1</link><pubDate>Mon, 17 Jan 2022 07:38:19 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:bb90cf66-cdc5-428c-923e-3abeda8814b4</guid><dc:creator>Stephan Walter</dc:creator><description>&lt;p&gt;Hi Kazi,&lt;/p&gt;
&lt;p&gt;Thank you for the quick response.&lt;/p&gt;
&lt;p&gt;I think I got confused by the behaviour of the nRF53, as that is influenced by whether the debugger is connected or other HFCLK peripherals are active.&lt;/p&gt;
&lt;p&gt;The problem with the SPIM not being triggered seems to be erratum 135. The workaround does fix the problem.&lt;/p&gt;
&lt;p&gt;As to my question 4:&lt;/p&gt;
&lt;blockquote&gt;
&lt;p&gt;The same section in the specification also says that the SENSE fields must be set correctly, but it seems not to be necessary.&lt;/p&gt;
&lt;/blockquote&gt;
&lt;p&gt;Please ignore this, I have now seen the case where there is no event triggered when the SENSE field is wrong.&lt;/p&gt;
&lt;p&gt;So I will now do the following:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;use GPIOTE.LATENCY=LowPower&lt;/li&gt;
&lt;li&gt;use default low-power submode&lt;/li&gt;
&lt;li&gt;always set SENSE field correctly for GPIOTE edge events&lt;/li&gt;
&lt;li&gt;implement workaround for SPIM4 erratum 135&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;I appreciate your other explanations.&lt;/p&gt;
&lt;p&gt;Best regards,&lt;/p&gt;
&lt;p&gt;--Stephan Walter&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF53 DPPI and low-power/low-latency</title><link>https://devzone.nordicsemi.com/thread/347798?ContentTypeID=1</link><pubDate>Fri, 14 Jan 2022 14:48:40 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:73f8aa27-0fe4-4252-8b31-7313a0e1a241</guid><dc:creator>Kazi Afroza Sultana</dc:creator><description>&lt;p&gt;Hello Stephan,&lt;/p&gt;
&lt;p&gt;Here are the answers to your questions:&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;1. Is it expected behavior that an LFCLK peripheral can&amp;#39;t trigger an HFCLK peripheral, such as in my case?&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;No. The peripheral does not know where the PPI signals originate from. The HF clock is controlled automatically. So, it&amp;#39;s not a problem when HFCLK is not running, SPIM should request this (HFCLK) automatically whenever needed.&amp;nbsp;&amp;nbsp;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;As you said Real-time clock runs from the LF clock and this again triggers the HF clock peripheral when needed. This is how every application should work. The Low-frequency clock and its correspondence peripheral (RTC) consume 1uA range current. So, it works by default when the chip is in idle mode and controls the timing of the application. And as I said before HF clock peripherals start working based on need as they consume current in the 1mA range.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;2. What is the relationship or difference between CONSTLAT sub-mode and GPIOTE.LATENCY=LowPower?&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;I don&amp;#39;t think there is any relationship. Constant latency will keep HFCLK/HFINT running to guarantee short/consistent wakeup time for the System from Sleep mode to ON.&amp;nbsp;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;GPIOTE LowPower is related to how often the peripheral will check the state of the pin, so you will need to have a longer hold time for the signal to be detected. Power consumption is low.&amp;nbsp;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;I have asked our team to know How the internal works to detect the signal. I will let you know when will get the answer.&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;strong&gt;3.&lt;/strong&gt; &lt;strong&gt;The specification states in section 7.14.4: &amp;quot;CONFIG.POLARITY=Toggle is not supported for LATENCY=LowPower.&amp;quot; Does this apply to both event and task modes or only to event mode?&lt;/strong&gt;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;Only in Event mode.&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;4. The same section in the specification also says that the SENSE fields must be set correctly, but it seems not to be necessary. The reason for asking this is that the Zephyr GPIO implementation alters this field in several places, and I found it error-prone to always have to set it after e.g. calling gpio_pin_interrupt_configure. What exactly happens if the SENSE field is not as expected when GPIOTE is in low-power mode?&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;This question may not relevant to other problems. However, you can follow the Zephyr implementation of the GPIO interrupts, and use &lt;span&gt;CONFIG_GPIO_NRF_INT_EDGE_USING_SENSE=y&lt;/span&gt; for low power operation.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;I hope it helps.&lt;/p&gt;
&lt;p&gt;Feel free to ask if you would like to know more.&lt;/p&gt;
&lt;p&gt;Best Regards,&lt;/p&gt;
&lt;p&gt;Kazi Afroza Sultana&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;strong&gt;&amp;nbsp;&lt;/strong&gt;&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF53 DPPI and low-power/low-latency</title><link>https://devzone.nordicsemi.com/thread/347708?ContentTypeID=1</link><pubDate>Fri, 14 Jan 2022 09:24:52 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:3d3dbe39-b938-4d0e-9f2d-c9257f7e05b3</guid><dc:creator>Kazi Afroza Sultana</dc:creator><description>&lt;p&gt;Hello Stephan,&lt;/p&gt;
&lt;p&gt;I have been working on your questions. I will come to you with the answers shortly.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Best Regards,&lt;/p&gt;
&lt;p&gt;Kazi Afroza Sultana&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>