[Basic Question] The speed of nRF51822 when executing instructions

RE: [Basic Question] The speed of nRF51822 when executing instructions

MANGO — Sun, 26 Jul 2015 08:24:25 GMT

I didn't thought about the ARM 6M reference manual. Thanks for letting me know.

About Q4, it sure is slow when comparing with the baud rate (115200) and time of one cycle.

However, let me change the question a little bit.

Suppose I attached a 3-axis digital gyroscope (L3GD20 for example) to the PCA10001.

Using SPI, with the clock speed of 10 MHz, reading a value will take 1.6 * 10^-8 sec.

(Since it uses 16 cycles.) After reading it, it need extra calculation to use it.

However, since the nRF51822 does not have FPU (Floating Point Unit),

I expected that the calculating time will be longer than 1.6 * 10^-8 sec.

As you said, multiply will take much longer and if the program uses floating points, I thought it will take more.

So, in this case, won't there be a slight delay to earn the value?

Chinook — Sun, 26 Jul 2015 07:54:52 GMT

Exact timings of instructions execution are given in the Cortex-M0 Technical Reference Manual. Taken branches execute in three cycles. Loads and stores add one cycle to the number of registers loaded/stored, pops loading pc take 3 additional cycles. For loads and stores you also have to add number of wait states for peripheral accesses. In my belief it's 2 wait states for all Nordic peripherals except RTC, for that it's 3 wait states. All other instructions including mul (nRF51 uses fast multiplier option) take 1 cycle. You can easily measure execution time of a sequence of instructions using a timer. Start a timer with zero prescaler and trigger capture tasks just before and after the instruction sequence, then subtract corresponding captured values and subtract 4 for one of the TASKS_CAPTURE accesses.
nRF51 runs at a fixed frequency of 16MHz, so instruction execution time is N/16 uS, where N is the duration of execution stage of that instruction.
nRF51 has no wait states for RAM (except for conflicting accesses) and FLASH (except during program or erase) accesses, pipeline stages perfectly overlap and so you don't have to bother with the pipeline.

RK — Sun, 26 Jul 2015 06:20:54 GMT

no - many instructions take 1 cycle, some take more, multiply takes quite a few and the load store multiple takes time depending on how many registers you're stacking. That's all in the ARM 6M reference manual.
One cycle is 1/16 microsecond and many instructions take one cycle. They used 14 because there's overhead in the rest of the loop to make an accurate delay (or not so accurate if you read other posts)
no you don't need to consider the pipeline. With the nRF52 you do have to consider the wait states on the flash and the pipeline comes into play there as it may stall, also the write buffer introduces cycles of delay here and there, the nrf51 doesn't have those issues.
I have no idea and don't really understand the question and UART rates are so much slower than the clock frequency of the chip I can't see it would matter.