clarification of PAN#73 (v3 TIMER PPI sleep issues) workaround

RE: clarification of PAN#73 (v3 TIMER PPI sleep issues) workaround

Susheel Nuguru — Wed, 05 Aug 2015 06:59:58 GMT

My description 2) explains this behavior. The workaround will also force to switch a voltage regulator on , that is why it was required to set this register to zero when not sleeping or not using timer events to trigger GPIOTE or RTC tasks

RE: clarification of PAN#73 (v3 TIMER PPI sleep issues) workaround

Paolo D — Tue, 04 Aug 2015 17:44:32 GMT

I measured the current consumption on the PCA10028 development board with a rev 3 chip. When in sleep mode, setting the timer register for the workaround to 1, without enabling the timer or doing anything else with it, increases the current consumption by 290uA.

RE: clarification of PAN#73 (v3 TIMER PPI sleep issues) workaround

Susheel Nuguru — Mon, 03 Aug 2015 06:56:59 GMT

The Anomaly apply only when in sleep mode and if TIMER events are channeled to gpiote or RTC through PPI (not necessarily configured just before the sleep)
If the chip is in normal (or system on) mode then no difference in power consumption. But if in sleep mode and not using Timer events to trigger GPIOTE or RTC tasks, then there will be unnecessary increase in power consumption.

The registers are undocumented for a good reason. And hence not available in header files. It is always good to explain this in comments giving links to PAN in your code if possible irrespective of if the register is documented or not(or available in header or not)