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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Complex SPI transactions with PPI compatible with Zephyr?</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/85719/complex-spi-transactions-with-ppi-compatible-with-zephyr</link><description>I have been trying to understand how we can use the PPI system to bypass extra callback handlers and threads in Zephyr to retrieve data from external SPI device based on external pin trigger. 
 So far my understanding of the PPI system is it can hold</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Mon, 14 Mar 2022 09:42:19 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/85719/complex-spi-transactions-with-ppi-compatible-with-zephyr" /><item><title>RE: Complex SPI transactions with PPI compatible with Zephyr?</title><link>https://devzone.nordicsemi.com/thread/357883?ContentTypeID=1</link><pubDate>Mon, 14 Mar 2022 09:42:19 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:d474dfa6-0959-4a2e-986c-2760f9e305ff</guid><dc:creator>Vidar Berg</dc:creator><description>&lt;p&gt;That is good news. Thank you for the update.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Complex SPI transactions with PPI compatible with Zephyr?</title><link>https://devzone.nordicsemi.com/thread/357845?ContentTypeID=1</link><pubDate>Mon, 14 Mar 2022 08:49:57 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:b3b66e8c-77dc-4f57-9229-569f4c4d5413</guid><dc:creator>Kyrre Aalerud</dc:creator><description>&lt;p&gt;You are correct, this can be done in a single operation with 1 dummy byte in receive buffer and 1 byte length&amp;nbsp;set in&amp;nbsp;tx_length. It was a mistake on my part assuming the CS needed deasserting between the transfers. This is true for the memory chip but not the sensor that we are using and where we want to optimize. It is thus possible with a single transaction.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Complex SPI transactions with PPI compatible with Zephyr?</title><link>https://devzone.nordicsemi.com/thread/357831?ContentTypeID=1</link><pubDate>Mon, 14 Mar 2022 08:27:32 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:49fed2b3-4004-4670-afea-ea1b0e4f8aa8</guid><dc:creator>Vidar Berg</dc:creator><description>[quote user=""]an address to the external device from the first tx buffer in the set, while ignoring the reception, having a NULL rx buffer before going on to the second set of buffers where the tx buffer is NULL and rx buffer is now valid and a count tells it to receive a set of data values.[/quote]
&lt;p&gt;What is the reason you can&amp;#39;t set this up as a single transfer? Is it because you don&amp;#39;t want to waste RX and TX buffers, or is it because you need to de-assert the CS line between these 2 transactions?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Complex SPI transactions with PPI compatible with Zephyr?</title><link>https://devzone.nordicsemi.com/thread/357813?ContentTypeID=1</link><pubDate>Mon, 14 Mar 2022 07:15:27 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:35805996-36a5-45b1-b21b-2a005ded1dfb</guid><dc:creator>Kyrre Aalerud</dc:creator><description>&lt;p&gt;This is exactly what I am describing, but it handles a single transfer only. The complex function of multiple tx and rx buffers and events to handle a potential setup or address in external unit is handled by the spi library and interrupt handler and as such is incapable of handling this via ppi and not involving the cpu.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Complex SPI transactions with PPI compatible with Zephyr?</title><link>https://devzone.nordicsemi.com/thread/357743?ContentTypeID=1</link><pubDate>Fri, 11 Mar 2022 16:38:48 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:7b80c6e2-3614-49f7-afc5-f72961744aac</guid><dc:creator>Vidar Berg</dc:creator><description>&lt;p&gt;Hello,&lt;/p&gt;
&lt;p&gt;For the scenario you outline you will likely need to work work with the nrfx driver APIs directly. There you have the &lt;a href="https://developer.nordicsemi.com/nRF_Connect_SDK/doc/latest/nrfx/drivers/spim/driver.html#c.nrfx_spim_xfer"&gt;nrfx_spim_xfer()&lt;/a&gt; function which lets you set up repeated TXRX transfers with auto increment of the RX and TX pointer (easyDMA list feature) and optionally with the END interrupt disabled (&lt;span&gt;NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER&lt;/span&gt;).&lt;/p&gt;
&lt;p&gt;Note that when using the &lt;span&gt;NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER&lt;/span&gt; flag, you can connect the END event via PPI to a TIMER in counter mode to keep track how many transfers have been completed.&lt;/p&gt;
&lt;p&gt;The Zephyr &lt;a href="https://developer.nordicsemi.com/nRF_Connect_SDK/doc/1.9.1/zephyr/samples/boards/nrf/nrfx/README.html"&gt;nrfx use example&lt;/a&gt; demonstrates how you can use nrfx drivers in the SDK.&lt;/p&gt;
&lt;p&gt;Best regards,&lt;/p&gt;
&lt;p&gt;Vidar&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>