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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Recommended Footprint nRF9160</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/87146/recommended-footprint-nrf9160</link><description>Hi, 
 
 The Evaluation board seems to have a footprint for nRF9160 non conventional. 
 The middle on TopLayer is a sort of Grid connected to the GND and Track to link Vias t Inner GND Plane. 
 
 Is this sort of connection recommended for some reason?</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Sat, 09 Dec 2023 22:03:18 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/87146/recommended-footprint-nrf9160" /><item><title>RE: Recommended Footprint nRF9160</title><link>https://devzone.nordicsemi.com/thread/459598?ContentTypeID=1</link><pubDate>Sat, 09 Dec 2023 22:03:18 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:857e04c5-c99a-41f2-9935-577dd7fe5149</guid><dc:creator>Timaxusa</dc:creator><description>&lt;p&gt;Did you guys end up finding solution?&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Recommended Footprint nRF9160</title><link>https://devzone.nordicsemi.com/thread/364433?ContentTypeID=1</link><pubDate>Fri, 22 Apr 2022 10:48:26 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:a9ca36ea-9190-47b8-83a0-27de0b62f873</guid><dc:creator>ketiljo</dc:creator><description>&lt;p&gt;There&amp;#39;s no other reason for the grind under the module than to improve solderability as a ground plane may take more time to heat properly. If you solder process allows for it, is should be ok.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;The aperture for the paste stencil may need reduction, depending on the thickness of the stencil and the process.&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Recommended Footprint nRF9160</title><link>https://devzone.nordicsemi.com/thread/364191?ContentTypeID=1</link><pubDate>Thu, 21 Apr 2022 11:00:40 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:e5ced3e6-6c9b-4b3f-830a-4e849c3f72ee</guid><dc:creator>Craig12</dc:creator><description>&lt;p&gt;I&amp;#39;m also interested to hear a response from Nordic on these questions. We did a small pilot run of 50 boards last year using the Altium Designer footprint provided in PCA10090-nRF9160 Development Board 1_0_0.&amp;nbsp; Our thoughts are the solder paste apertures for the internal 5 x 7 grid was too large and was effecting our yield.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>