RTC in repeat mode with no CPU involvement ( SDK v13 )

RE: RTC in repeat mode with no CPU involvement ( SDK v13 )

bryanhsieh — Thu, 05 May 2022 15:23:21 GMT

Thanks for the detailed answer. I was able to implement the above with the RTC interrupt disabled as clarified.

RE: RTC in repeat mode with no CPU involvement ( SDK v13 )

Jørgen Holmefjord — Thu, 28 Apr 2022 11:24:15 GMT

Hi,

[quote user="bryanhsieh"]The main thing I wanted to check was whether the compare flag would get retriggered once the counter of the RTC has been cleared via PPI, but looking at the hardware implementation of the RTC which is slightly different to other peripherals, it looks like event flag is latched by the register so has to be manually cleared by the CPU.[/quote]

The event registers are usually latched when the event signal is generated by the HW peripheral, and needs to be cleared by the CPU. However, the peripheral can normally regenerate the signal event if the register is already set, see Events:

"Events can be generated by the peripheral even when the event register is set to '1'."

[quote user="bryanhsieh"]By disabling the interrupt wouldn't the RTC stop running after the first compare event?[/quote]

The event register needs to be cleared by the CPU in order to trigger a new interrupt, see Interrupts. If interrupts are disabled, and the events are connected to tasks through PPI, there is no need to clear the event registers for a new event to be generated.

[quote user="bryanhsieh"]

My current implementation ( see attached file ) is this, I have 3 PPIs, one to trigger the ADC start task and forked to clear RTC counter.

Another PPI to trigger the start sample task on ADC started event.

And the final PPI to trigger the stop task on events end event.

The RTC interrupt calls cc_set which clears the compare flag.

The ADC interrupt clears each individual event and in the case of ADC stopped it uninits and restarts the ADC module before initializing it.

For sanity check, with the above implementation would you agree that the ADC sampling would be accurate as long as the compare flag is cleared and ADC result is moved to an array before the next sampling period is up?

[/quote]

Most likely it will work and give accurate sampling time, but there may occur a race condition/issue in case your interrupt handling is delayed long enough. The RTC events/interrupts may be disabled right before the RTC hits the CC value, and enabled again after the CC value is passed. Since you do not clear the RTC in the event handler, the RTC will run until it overflows and hit the CC value value a second time before the event is generated.

Best regards,
Jørgen

RE: RTC in repeat mode with no CPU involvement ( SDK v13 )

bryanhsieh — Wed, 27 Apr 2022 15:18:33 GMT

devzone.nordicsemi.com/.../6661.main.c

Thanks Jorgen.

The main thing I wanted to check was whether the compare flag would get retriggered once the counter of the RTC has been cleared via PPI, but looking at the hardware implementation of the RTC which is slightly different to other peripherals, it looks like event flag is latched by the register so has to be manually cleared by the CPU. By disabling the interrupt wouldn't the RTC stop running after the first compare event?

My current implementation ( see attached file ) is this, I have 3 PPIs, one to trigger the ADC start task and forked to clear RTC counter.

Another PPI to trigger the start sample task on ADC started event.

And the final PPI to trigger the stop task on events end event.

The RTC interrupt calls cc_set which clears the compare flag.

The ADC interrupt clears each individual event and in the case of ADC stopped it uninits and restarts the ADC module before initializing it.

RE: RTC in repeat mode with no CPU involvement ( SDK v13 )

Jørgen Holmefjord — Wed, 27 Apr 2022 13:52:57 GMT

Hi,

It is not required to call nrf_drv_rtc_cc_set() in the event handler to set the CC value, the reason that this function is called in the handler is to re-enable the event and interrupts. In the IRQ Handler in the RTC driver, the events and interrupts are disabled when the COMPARE event is detected:

nrf_rtc_event_disable(p_reg,int_mask);
nrf_rtc_int_disable(p_reg,int_mask);

If you disable the interrupt and clear the RTC through PPI (fork), the code in the interrupt handler will not be run, and the CC register will not be changed.

Note that you will likely not be able to achieve low power SAADC sampling and sampling with precise timing at the same time. The SAADC will have high current consumption when it is STARTED, which is required in order to sample through PPI. We have some low power examples, but this will stop the SAADC between each sample, and it must be restarted by the software.

You may be able to achieve something semi-precise and low power by triggering the START task through PPI and connect the SAADC STARTED event to the SAMPLE task, but I have not tested this. This approach is also not supported by the SAADC driver, so you would need to write your own custom implementation. In this solution, you need to make sure that the CPU provides a new buffer for the SAADC to sample to between the STARTED event and the next triggering of START task over PPI, to prevent the previous buffer from being overwritten.

Best regards,
Jørgen