What is the minimum entry latency of a late-arriving exception?

RE: What is the minimum entry latency of a late-arriving exception?

Susheel Nuguru — Wed, 18 May 2022 16:52:35 GMT

Hi,

We have not changed any Chip specific implementation for the behavior of NVIC and the latencies that occur after the interrupt is pended to NVIC (including late arriving). The maximum latencies are same (6 cycles) as with tailchaining when FPU is not enabled.

RE: What is the minimum entry latency of a late-arriving exception?

Susheel Nuguru — Sun, 15 May 2022 12:43:51 GMT

I haven't got any information back on this, sorry for delays and thanks for your patience. i will ping my colleague again and update this thread when I receive some info.

RE: What is the minimum entry latency of a late-arriving exception?

Susheel Nuguru — Wed, 11 May 2022 10:54:03 GMT

I understand the curiosity, unfortunately I could not get hold of the correct person who can answer this today, I will try again tomorrow. Thanks a ton for your patience.

RE: What is the minimum entry latency of a late-arriving exception?

car — Tue, 10 May 2022 08:48:40 GMT

Thanks for looking into it. Even if Nordic implemented nothing special here, it would be good to know what the minimum latency is. I guess it could be the same six cycles as with tail chaining, but ARM doesn't say anything about it (probably because it is implementation dependent).

RE: What is the minimum entry latency of a late-arriving exception?

Susheel Nuguru — Mon, 09 May 2022 18:50:17 GMT

I do not think we have implemented any minimum value for keeping the interrupt latency predictable. But I am unsure of this, so I need to verify this with the architects. Will be back to you with more info when I find out some.