<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>NRF52 pcb design</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/8806/nrf52-pcb-design</link><description>during the pcb design of nrf52, is it compulsory to totally copy your reference pcb layout . since our case need to design a small size device, so i have to modify the pcb design(not change the component ,just rearrange some components) and make it tight</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Fri, 09 Dec 2016 15:26:45 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/8806/nrf52-pcb-design" /><item><title>RE: NRF52 pcb design</title><link>https://devzone.nordicsemi.com/thread/32325?ContentTypeID=1</link><pubDate>Fri, 09 Dec 2016 15:26:45 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:ae5e944c-2114-4c00-9217-a90a3ea3db39</guid><dc:creator>Ole Bauck</dc:creator><description>&lt;p&gt;You should have a ground plane under the RF section. On nRF52 this can be on any of the layers. It is most common to use the second layer as a ground layer in 4 layer design. Then you can route signals on the third or fourth layer under the RF section.&lt;/p&gt;
&lt;p&gt;On nRF51, the story is different. There the ground layer has to be on the bottom layer.&lt;/p&gt;
&lt;p&gt;If you have questions that are not directly related to the original question, please make a new question on the forum rather than to post it as an answer to the original question. This will make it easier for others to find the right question and answers on the forum.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: NRF52 pcb design</title><link>https://devzone.nordicsemi.com/thread/32324?ContentTypeID=1</link><pubDate>Fri, 09 Dec 2016 11:17:28 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:573b9a78-7ba9-447b-94cd-4756f69766de</guid><dc:creator>Charlie Skilbeck</dc:creator><description>&lt;p&gt;I notice that the bottom ground plane extends under the RF section, but I was under the impression that there should not be any ground plane there. The other layer ground planes have cutouts but not the bottom one - can someone from Nordic explain the reasoning?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: NRF52 pcb design</title><link>https://devzone.nordicsemi.com/thread/32323?ContentTypeID=1</link><pubDate>Wed, 26 Aug 2015 07:09:35 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:93fdc000-fe47-405d-bf4e-5ccdc8c54dde</guid><dc:creator>ketiljo</dc:creator><description>&lt;p&gt;You should follow the reference layout for the RF section, unless you have a very good reason for not doing so. For the rest of the design, just follow common sense, like placing decopling caps close to the relevant pins etc.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: NRF52 pcb design</title><link>https://devzone.nordicsemi.com/thread/32321?ContentTypeID=1</link><pubDate>Wed, 26 Aug 2015 05:37:56 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:48cdca44-a5c7-4e45-b4ef-4c3c94e171e9</guid><dc:creator>oliverhu</dc:creator><description>&lt;p&gt;is it necessary to follow the reference layout? Why does this page advise to follow reference layout ?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: NRF52 pcb design</title><link>https://devzone.nordicsemi.com/thread/32322?ContentTypeID=1</link><pubDate>Fri, 21 Aug 2015 12:13:13 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:220e5cb9-1bfc-4ebf-959f-1f6ebc523271</guid><dc:creator>Lakerno</dc:creator><description>&lt;p&gt;other than that, is it necessary to follow the reference layout? Why does this page advise to follow reference layout ? &lt;a href="http://infocenter.nordicsemi.com/index.jsp?topic=%2Fnrf52.v1.7%2FChunk1047795221.html&amp;amp;cp=1_1_0_48&amp;amp;anchor=concept_aqp_fd1_fq"&gt;infocenter.nordicsemi.com/index.jsp&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;Again, it appears that the reference layout is not very small, and some space is wasted here and there . For eg, if you look at the reference layout in Fig 5,6 in the page below , you can see some space is wasted in top,bottom,sides. Why not make a more compact design?&lt;/p&gt;
&lt;p&gt;&lt;a href="http://infocenter.nordicsemi.com/index.jsp?topic=%2Fnrf52.v1.7%2FChunk1047795221.html&amp;amp;cp=1_1_0_48&amp;amp;anchor=concept_aqp_fd1_fq"&gt;infocenter.nordicsemi.com/index.jsp&lt;/a&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: NRF52 pcb design</title><link>https://devzone.nordicsemi.com/thread/32320?ContentTypeID=1</link><pubDate>Fri, 21 Aug 2015 11:22:38 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:cababf21-d988-444e-b027-c976e6d0a9b5</guid><dc:creator>ketiljo</dc:creator><description>&lt;p&gt;Just be careful with the how you do the grounding of the shunt capacitor. If you look at the reference layout, you&amp;#39;ll see that it&amp;#39;s connected to the ground pin of the nRF52 and not directly to the ground plane. This is done on purpose to have a bit of track inductance (ca 0.7 nH). The track and the cap forms a filter that attenuates the second harmonic.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: NRF52 pcb design</title><link>https://devzone.nordicsemi.com/thread/32318?ContentTypeID=1</link><pubDate>Wed, 19 Aug 2015 09:15:27 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:add75dc4-6833-46cc-8a9e-fd69c927ee4f</guid><dc:creator>Lakerno</dc:creator><description>&lt;p&gt;In one of my previous question , Øyvind Karlsen indicated that T network is inferred using the wiring. In this case, if the layout is modified compared to the reference layout, will it affect the design/component values in the reference design in any manner?&lt;/p&gt;
&lt;p&gt;&lt;a href="https://devzone.nordicsemi.com/question/44555/recommended-chip-antenna-debugger-for-nrf52-based-design/"&gt;devzone.nordicsemi.com/.../&lt;/a&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: NRF52 pcb design</title><link>https://devzone.nordicsemi.com/thread/32319?ContentTypeID=1</link><pubDate>Wed, 19 Aug 2015 07:43:08 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:c2fec32f-410a-48e5-bb5a-01e19820e148</guid><dc:creator>Michael Dietz</dc:creator><description>&lt;p&gt;Yes, this is OK. You should have no problem doing this. Since the nRF52 has an on-chip balun there isn&amp;#39;t much high frequency stuff you can mess up. But as a rule dont touch any of the high frequency (2.4 GHz) components unless you really know what your doing. So if you are using a reference example that has a pi tuning network for the antenna dont mess with that.&lt;/p&gt;
&lt;p&gt;but clocks, decoupling capacitors, dc/dc converters no problem.. just be careful with antenna/radio stuff.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: NRF52 pcb design</title><link>https://devzone.nordicsemi.com/thread/32317?ContentTypeID=1</link><pubDate>Wed, 19 Aug 2015 04:55:00 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:2af61a9b-b07a-4fd2-8f7f-3c263ca7e61a</guid><dc:creator>Lakerno</dc:creator><description>&lt;p&gt;same question here. Need the reference layout be exactly copied to my design? or can change layout and keep the components the same?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>